公开(公告)号：US20160118096A1

公开(公告)日：2016-04-28

申请号：US14989678

申请日：2016-01-06

Applicant: Micron Technology, Inc.

Inventor： Marco-Domenico Tiburzi ,  Giulio-Giuseppe Marotta

IPC: G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C7/22

CPC classification number: G11C7/12 ,  G11C5/141 ,  G11C5/148 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C11/56

Abstract: Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled to a plurality of memory cells and is configured to provide access to the plurality of memory cells responsive to a biasing condition of the signal line. The memory array also includes a signal line driver coupled to the signal line, the signal line driver configured to provide a biasing signal to the signal line and to provide a preemphasis in the biasing signal responsive to a control signal. The control signal is responsive to an operating condition.

Abstract translation: 公开了用于偏置存储器阵列中的信号线的装置，电路和方法。 在一个这样的示例中，存储器阵列包括耦合到多个存储器单元的信号线，并且被配置为响应于信号线的偏置条件来提供对多个存储器单元的访问。 存储器阵列还包括耦合到信号线的信号线驱动器，信号线驱动器被配置为向信号线提供偏置信号，并且响应于控制信号在偏置信号中提供预加重。 控制信号响应于操作状态。

公开(公告)号：US11978680B2

公开(公告)日：2024-05-07

申请号：US17534973

申请日：2021-11-24

Applicant: Micron Technology, Inc.

Inventor： Kenneth William Marr ,  Chiara Cerafogli ,  Michele Piccardi ,  Marco-Domenico Tiburzi ,  Eric Higgins Freeman ,  Joshua Daniel Tomayer

IPC: H01L21/66 ,  G01B7/16 ,  G01L1/16 ,  G01L1/18 ,  H01L29/84

CPC classification number: H01L22/34 ,  G01B7/18 ,  G01L1/16 ,  G01L1/18 ,  H01L29/84

Abstract: A microelectronic chip device includes a semiconductor substrate and multiple on-chip strain sensors (OCSSs) constructed on the substrate at various locations of the substrate. The OCSSs may each include multiple piezoresistive devices configured to sense a strain at a location of the various locations and produce a strain signal representing the strain at that location. A strain measurement circuit may also be constructed on the semiconductor substrate and configured to measure strain parameters from the strain signals produced by the OCSSs. The strain parameters represent the strains at the various location. Values of the strain parameters can be used for analysis of mechanical stress on the chip device.

公开(公告)号：US20200211914A1

公开(公告)日：2020-07-02

申请号：US16294469

申请日：2019-03-06

Applicant: Micron Technology, Inc.

Inventor： Kenneth William Marr ,  Chiara Cerafogli ,  Michele Piccardi ,  Marco-Domenico Tiburzi ,  Eric Higgins Freeman ,  Joshua Daniel Tomayer

IPC: H01L21/66 ,  G01B7/16

Abstract: A microelectronic chip device includes a semiconductor substrate and multiple on-chip strain sensors (OCSS s) constructed on the substrate at various locations of the substrate. The OCSSs may each include multiple piezoresistive devices configured to sense a strain at a location of the various locations and produce a strain signal representing the strain at that location. A strain measurement circuit may also be constructed on the semiconductor substrate and configured to measure strain parameters from the strain signals produced by the OCSSs. The strain parameters represent the strains at the various location. Values of the strain parameters can be used for analysis of mechanical stress on the chip device.

公开(公告)号：US10553289B1

公开(公告)日：2020-02-04

申请号：US16161256

申请日：2018-10-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca De Santis ,  Marco-Domenico Tiburzi

IPC: G11C16/26 ,  G11C16/34 ,  G11C11/409 ,  G11C7/06 ,  G11C16/28 ,  G11C11/56 ,  G11C16/04 ,  G11C7/14 ,  G11C29/50

Abstract: Methods of operating a memory including applying an intermediate read voltage to a selected access line for a read operation, adding noise to a sensing operation while applying the intermediate read voltage, determining a value indicative of a number of memory cells of a plurality of memory cells connected to the selected access line that are activated in response to applying the intermediate read voltage to the selected access line, and determining an expected data age of the plurality of memory cells in response to the value indicative of the number of memory cells of the plurality of memory cells that are activated in response to applying the intermediate read voltage to the selected access line.

公开(公告)号：US10134454B2

公开(公告)日：2018-11-20

申请号：US15895290

申请日：2018-02-13

Applicant: Micron Technology, Inc.

Inventor： Marco-Domenico Tiburzi ,  Giulio-Giuseppe Marotta

IPC: G11C7/00 ,  G11C7/12 ,  G11C8/10 ,  G11C8/08 ,  G11C7/22 ,  G11C8/18 ,  G11C5/14 ,  G11C11/56

Abstract: Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled to a plurality of memory cells and is configured to provide access to the plurality of memory cells responsive to a biasing condition of the signal line. The memory array also includes a signal line driver coupled to the signal line, the signal line driver configured to provide a biasing signal to the signal line and to provide a preemphasis in the biasing signal responsive to a control signal. The control signal is responsive to an operating condition.

公开(公告)号：US10089359B2

公开(公告)日：2018-10-02

申请号：US15253965

申请日：2016-09-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca De Santis ,  Giulio G. Marotta ,  Marco-Domenico Tiburzi ,  Tommaso Vali ,  Frankie F. Roohparvar ,  Agostino Macerola

IPC: G06F11/263 ,  G06F17/30 ,  G06F3/06 ,  G11C16/06 ,  G11C7/10 ,  G11C15/04 ,  G11C16/04 ,  G06F7/20 ,  G06F12/0802 ,  G11C29/50

Abstract: Memory devices for facilitating pattern matching and having an array of memory cells, a plurality of key registers to store a representation of a key word, and a plurality of multiplexers, each multiplexer of the plurality of multiplexers to select a representation of a bit from a key register of the plurality of key registers to compare to data stored in the array of memory cells.

公开(公告)号：US09646662B2

公开(公告)日：2017-05-09

申请号：US14989678

申请日：2016-01-06

Applicant: Micron Technology, Inc.

Inventor： Marco-Domenico Tiburzi ,  Giulio-Giuseppe Marotta

IPC: G11C16/06 ,  G11C8/08 ,  G11C8/10 ,  G11C7/12 ,  G11C7/22 ,  G11C8/18

CPC classification number: G11C7/12 ,  G11C5/141 ,  G11C5/148 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C11/56

Abstract: Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled to a plurality of memory cells and is configured to provide access to the plurality of memory cells responsive to a biasing condition of the signal line. The memory array also includes a signal line driver coupled to the signal line, the signal line driver configured to provide a biasing signal to the signal line and to provide a preemphasis in the biasing signal responsive to a control signal. The control signal is responsive to an operating condition.

公开(公告)号：US09570172B2

公开(公告)日：2017-02-14

申请号：US14733603

申请日：2015-06-08

Applicant: Micron Technology, Inc.

Inventor： Marco-Domenico Tiburzi ,  Giulio-Giuseppe Marotta

IPC: G11C11/00 ,  G11C13/00 ,  G11C7/12

CPC classification number: G11C13/0097 ,  G11C7/12 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2013/0085 ,  G11C2013/0088 ,  G11C2213/79

Abstract: Apparatuses and methods are described, such as those involving driver circuits that are configured to provide reset and set voltages to different variable state material memory cells in an array at the same time. Additional apparatuses, and methods are described.

Abstract translation: 描述了这样的装置和方法，例如那些涉及被配置为同时向阵列中的不同可变状态材料存储器单元提供复位和置位电压的那些。 描述附加的装置和方法。

公开(公告)号：US10515669B2

公开(公告)日：2019-12-24

申请号：US16118724

申请日：2018-08-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Agostino Macerola ,  Marco-Domenico Tiburzi ,  Stefano Perugini

IPC: G11C5/14 ,  G05F3/16 ,  G06F1/3203 ,  G06F1/3234 ,  G11C16/30 ,  G11C16/04

Abstract: Voltage generation circuits include a stage including a voltage driver having inputs connected to respective voltage nodes and a clock signal, and a stage capacitance having a first electrode connected to an output of the voltage driver and a second electrode connected to a voltage isolation device. The voltage driver might be configured to connect its output to receive a first voltage when the clock signal has a particular logic level and a voltage level of its output is less than a threshold, to connect its output to receive a second voltage greater than the first voltage when the clock signal has the particular logic level and the voltage level of its output is greater than the threshold, and to connect its output to receive a third voltage less than the first voltage when the clock signal has a different logic level.

公开(公告)号：US10388340B2

公开(公告)日：2019-08-20

申请号：US16165732

申请日：2018-10-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Marco-Domenico Tiburzi ,  Giulio-Giuseppe Marotta

IPC: G11C7/00 ,  G11C7/12 ,  G11C8/10 ,  G11C8/08 ,  G11C7/22 ,  G11C8/18 ,  G11C5/14 ,  G11C11/56

Abstract: Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled to a plurality of memory cells and is configured to provide access to the plurality of memory cells responsive to a biasing condition of the signal line. The memory array also includes a signal line driver coupled to the signal line, the signal line driver configured to provide a biasing signal to the signal line and to provide a preemphasis in the biasing signal responsive to a control signal. The control signal is responsive to an operating condition.