公开(公告)号：US20250118356A1

公开(公告)日：2025-04-10

申请号：US18751840

申请日：2024-06-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yasuhiro Takai ,  Shuichi Tsukada

IPC: G11C11/4093 ,  G11C11/4076

Abstract: Embodiments of the disclosure provide an apparatus comprising: first and second input transistors of a first type and first and second load transistors of a second type coupled in series, respectively; at least one resistor coupled to gate nodes of the load transistors; and first and second capacitive devices. Gate nodes of the first and second input transistors are coupled to first and second inputs, respectively. The first input transistor and the first load transistor are coupled to a first output. The second input transistor and the second load transistor are coupled to a second output. The gate nodes of the first and second load transistors are coupled to a bias voltage through the resistor. The first and second capacitive devices are coupled to the first and second inputs and to the gate nodes of the first and second load transistors, respectively.

公开(公告)号：US11705888B2

公开(公告)日：2023-07-18

申请号：US17086792

申请日：2020-11-02

Applicant: Micron Technology, Inc.

Inventor： Yasuo Satoh ,  Hiroki Takahashi ,  Shuichi Tsukada ,  Yuan He

IPC: H03K19/00 ,  H03H11/54 ,  H03H11/28

CPC classification number: H03H11/54 ,  H03H11/28 ,  H03K19/0005 ,  G11C2207/2254

Abstract: A memory device includes a terminal calibration circuit having at least one of a pull-down circuit or a pull-up circuit used in calibrating an impedance of a data bus termination. The memory device also includes a reference calibration circuit configured to generate a calibration current. The terminal calibration circuit can be configured to program an impedance of the least one of a pull-down circuit or a pull-up circuit based on the calibration current.

公开(公告)号：US20230170013A1

公开(公告)日：2023-06-01

申请号：US17700289

申请日：2022-03-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tetsuya Arai ,  Shuichi Tsukada ,  Shun Nishimura ,  Yoshinori Matsui

IPC: G11C11/4096 ,  G11C11/4093 ,  H03K19/003

CPC classification number: G11C11/4096 ,  G11C11/4093 ,  H03K19/00384

Abstract: Apparatuses including output drivers and methods for providing output data signals are described. An example apparatus includes a high logic level driver, a low logic level driver, and an intermediate logic level driver. The high logic level driver is provided a first voltage and provides a high logic level voltage to a data terminal when activated. The low logic level driver is provided a second voltage and provides a low logic level voltage to the data terminal when activated. The intermediate logic level driver is provided a third voltage having a magnitude that is between the first and second voltages, and provides an intermediate logic level voltage to the data terminal when activated. Each of the high, low, and intermediate logic level drivers are configured to be respectively activated based on one or more of a plurality of control signals.

公开(公告)号：US10529392B2

公开(公告)日：2020-01-07

申请号：US16418868

申请日：2019-05-21

Applicant: Micron Technology, Inc.

Inventor： Shuichi Tsukada

IPC: G11C7/02 ,  G11C7/10 ,  G11C5/14 ,  G11C11/4093 ,  G11C7/06 ,  G11C11/4074

Abstract: Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes: a first amplifier that provides first and second intermediate voltages responsive to first and second input voltages; first and second voltage terminals; a circuit node; a first transistor coupled between the first voltage terminal and the circuit node and is turned on responsive to at least one of the first and second intermediate voltages; a second amplifier including first and second inverters, at least one of the first and second inverters being coupled between the circuit node and the second voltage terminal; and first and second output nodes, the first output node being coupled to an input node of the first inverter and an output node of the second inverter, and the second output node being coupled to an output node of the first inverter and an input node of the second inverter.

公开(公告)号：US20190272858A1

公开(公告)日：2019-09-05

申请号：US16418868

申请日：2019-05-21

Applicant: Micron Technology, Inc.

Inventor： Shuichi Tsukada

IPC: G11C7/10 ,  G11C5/14 ,  G11C11/4093 ,  G11C7/06

Abstract: Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes: a first amplifier that provides first and second intermediate voltages responsive to first and second input voltages; first and second voltage terminals; a circuit node; a first transistor coupled between the first voltage terminal and the circuit node and is turned on responsive to at least one of the first and second intermediate voltages; a second amplifier including first and second inverters, at least one of the first and second inverters being coupled between the circuit node and the second voltage terminal; and first and second output nodes, the first output node being coupled to an input node of the first inverter and an output node of the second inverter, and the second output node being coupled to an output node of the first inverter and an input node of the second inverter.

公开(公告)号：US20190172507A1

公开(公告)日：2019-06-06

申请号：US16229266

申请日：2018-12-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenji Asaki ,  Shuichi Tsukada

IPC: G11C7/12 ,  H03K17/687

Abstract: Apparatuses and methods for providing bias signals in a semiconductor device are described. As example apparatus includes a power supply line configured to provide a supply voltage and further includes first and second nodes. An impedance element is coupled between the power supply line and the first node and a first transistor having a gate, a source coupled to the first node, and a drain coupled to the second node. A reference line is configured to provide a reference voltage. A second transistor has a gate, a source coupled to the reference line, and a drain. The gate and the drain of the second transistor are coupled to the gate of the first transistor.

公开(公告)号：US20180233180A1

公开(公告)日：2018-08-16

申请号：US15893398

申请日：2018-02-09

Applicant: Micron Technology, Inc.

Inventor： Shuichi Tsukada

IPC: G11C7/10 ,  G11C5/14 ,  G11C7/06

CPC classification number: G11C7/1084 ,  G11C5/14 ,  G11C7/02 ,  G11C7/065 ,  G11C7/1072 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/4074 ,  G11C11/4093

Abstract: Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes: a first amplifier that provides first and second intermediate voltages responsive to first and second input voltages; first and second voltage terminals; a circuit node; a first transistor coupled between the first voltage terminal and the circuit node and is turned on responsive to at least one of the first and second intermediate voltages; a second amplifier including first and second inverters, at least one of the first and second inverters being coupled between the circuit node and the second voltage terminal; and first and second output nodes, the first output node being coupled to an input node of the first inverter and an output node of the second inverter, and the second output node being coupled to an output node of the first inverter and an input node of the second inverter.

公开(公告)号：US20150063003A1

公开(公告)日：2015-03-05

申请号：US14473489

申请日：2014-08-29

Applicant: Micron Technology. Inc.

Inventor： Shuichi Tsukada

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2213/79 ,  H01L27/24

Abstract: A semiconductor device including: a resistive memory element; a data line electrically coupled to the resistive memory element; a control line; a power supply line; and a control circuit including a first constant current element, a first transistor, and a second transistor. In the control circuit, the first transistor has a gate coupled to the data line, one of a source and a drain coupled to the first constant current element, and the other one of the source and the drain coupled to the power supply line. The second transistor has a gate coupled to one of the source and the drain of the first transistor, one of a source and a drain coupled to the data line, and the other one of the source and the drain coupled to the control line.

Abstract translation: 一种半导体器件，包括：电阻性存储元件; 电耦合到所述电阻性存储元件的数据线; 控制线 电源线; 以及包括第一恒流元件，第一晶体管和第二晶体管的控制电路。 在控制电路中，第一晶体管具有耦合到数据线的栅极，耦合到第一恒流元件的源极和漏极之一，以及耦合到电源线的源极和漏极中的另一个。 第二晶体管具有耦合到第一晶体管的源极和漏极之一的栅极，耦合到数据线的源极和漏极中的一个，以及耦合到控制线的源极和漏极中的另一个。

公开(公告)号：US11132015B2

公开(公告)日：2021-09-28

申请号：US16271679

申请日：2019-02-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenji Asaki ,  Shuichi Tsukada

IPC: G06F1/08 ,  H03B5/12 ,  G06F1/28 ,  G06F1/06 ,  G06F13/16 ,  G06F13/00 ,  G06F1/04 ,  G06F1/10

Abstract: In some embodiments, clock input buffer circuitry and divider circuitry use a combination of externally-suppled voltages and internally-generated voltages to provide the various clock signals used by a semiconductor device. For example, a clock input buffer is configured to provide second complementary clock signals responsive to received first complementary clock signals using cross-coupled buffer circuitry coupled to a supply voltage and to drive the first complementary clock signals using driver circuitry coupled to an internal voltage. In another example, a divider circuitry may provide divided clock signals based on the second complementary clock signals via a divider coupled to the internal voltage and to drive the divided clock signals using driver circuitry coupled to the supply voltage. A magnitude of the supply voltage may be less than a magnitude of the internal voltage.

公开(公告)号：US10902892B2

公开(公告)日：2021-01-26

申请号：US16357085

申请日：2019-03-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shuichi Tsukada

IPC: H03F3/45 ,  G11C7/10 ,  H03F3/68

Abstract: Disclosed herein is an apparatus that includes first and second signal lines; a first differential amplifier having an inverting input node receiving an input signal, a non-inverting input node receiving a reference potential, and an output node connected to the first signal line; a second differential amplifier having an inverting input node receiving the reference potential, a non-inverting input node receiving the input signal, and an output node connected to the second signal line; a level shift circuit cross-coupled to the first and second signal lines; a first replica circuit connected to the first signal line; a second replica circuit connected to the second signal line; and a first switch circuit configured to activate one of the level shift circuit, the first replica circuit, and the second replica circuit.