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    SEMICONDUCTOR STRUCTURE
    11.
    发明申请
    SEMICONDUCTOR STRUCTURE 有权

    公开(公告)号：US20180102370A1

    公开(公告)日：2018-04-12

    申请号：US15837109

    申请日：2017-12-11

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Erh-Kun Lai

    IPC: H01L27/1157 ,  H01L21/28 ,  H01L27/11582 ,  H01L21/033

    CPC classification number: H01L27/1157 ,  H01L21/0332 ,  H01L21/28282 ,  H01L27/11582 ,  H01L28/00

    Abstract: A semiconductor structure and a method of manufacturing the same are provided. The semiconductor structure includes a stack including first conductive layers and first dielectric layers, a second conductive layer formed on the stack, openings through the second conductive layer and the stack, and through structures formed in the openings, respectively. Each through structure includes a memory layer, a gate dielectric layer, a channel layer, a dielectric material and a pad. The channel layer is isolated from the stack by the memory layer, the channel layer is isolated from the second conductive layer by the gate dielectric layer, and the memory layer and the gate dielectric layer have different compositions.

    Memory structure, method of operating the same, and method of manufacturing the same
    12.
    发明授权
    Memory structure, method of operating the same, and method of manufacturing the same 有权

    公开(公告)号：US09818760B1

    公开(公告)日：2017-11-14

    申请号：US15463109

    申请日：2017-03-20

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Erh-Kun Lai ,  Hsiang-Lan Lung

    IPC: G11C5/02 ,  H01L27/11582 ,  H01L27/1157 ,  G11C16/04 ,  G11C16/08

    CPC classification number: H01L27/11582 ,  G11C16/0466 ,  G11C16/0483 ,  H01L27/1157

    Abstract: A memory structure includes stacks, memory layers, channel layers, dielectric layers, and first conductive lines. Each stack includes a group of alternating conductive strips and insulating strips. The memory layers are conformally disposed on the stacks. The channel layers are conformally disposed on the memory layers. The dielectric layers are disposed on portions of the channel layers at first sides of the stacks and portions of the channel layers at second sides of the stacks. The first conductive lines are disposed along sidewalls of the stacks. The first conductive lines are isolated from the channel layers by the dielectric layers. One first conductive line disposed at the first side of one stack is isolated from one first conductive line disposed at the second side of the same stack and isolated from one first conductive line disposed at the second side of an adjacent stack.

    Memory structure
    14.
    发明授权
    Memory structure 有权
    内存结构

    公开(公告)号：US09537093B1

    公开(公告)日：2017-01-03

    申请号：US15044280

    申请日：2016-02-16

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Erh-Kun Lai ,  Hsiang-Lan Lung

    IPC: H01L29/02 ,  H01L45/00 ,  H01L27/24

    CPC classification number: H01L27/2481 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1675

    Abstract: A memory structure is disclosed. The memory structure comprises a phase change material layer, a first electrode, a second electrode, and conductive spacers. The second electrode and the first electrode are electrically connected to an upper surface and a lower surface of the phase change material layer respectively. The conductive spacers are separated from each other and on side surfaces of the phase change material layer.

    Abstract translation: 公开了一种存储器结构。 存储器结构包括相变材料层，第一电极，第二电极和导电间隔物。 第二电极和第一电极分别电连接到相变材料层的上表面和下表面。 导电间隔物彼此分离并在相变材料层的侧表面上分离。

    Semiconductor device and manufacturing method thereof
    15.
    发明授权
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号：US09437611B1

    公开(公告)日：2016-09-06

    申请号：US14629537

    申请日：2015-02-24

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Erh-Kun Lai

    IPC: H01L29/78 ,  H01L27/115 ,  H01L21/28 ,  H01L21/311 ,  H01L21/02 ,  H01L29/49 ,  H01L29/16 ,  H01L29/04

    CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L29/04 ,  H01L29/16 ,  H01L29/4234 ,  H01L29/4916

    Abstract: A semiconductor device and a manufacturing method of a semiconductor device thereof are provided. The manufacturing method includes the following steps. A bottom insulating layer is formed on a substrate. Two stacked structures are formed on the bottom insulating layer. Each of the stacked structures includes a plurality of gate layers, a plurality of gate insulating layers, a top insulating layer and a conductive mask layer. Each of the charge trapping structures includes a plurality of first dielectric layers and a plurality of second dielectric layers. Part of each of first dielectric layers is etched. Part of each of second dielectric layers is etched to expose part of the channel layer. A landing pad layer is formed on the conductive mask layer, the first dielectric layers and the second dielectric layers to connect the conductive mask layer and the channel layer.

    Abstract translation: 提供半导体器件及其半导体器件的制造方法。 该制造方法包括以下步骤。 底部绝缘层形成在基板上。 在底部绝缘层上形成两个堆叠结构。 每个堆叠结构包括多个栅极层，多个栅极绝缘层，顶部绝缘层和导电掩模层。 每个电荷俘获结构包括多个第一电介质层和多个第二电介质层。 每个第一介电层的一部分被蚀刻。 每个第二电介质层的一部分被蚀刻以暴露沟道层的一部分。 在导电掩模层，第一介电层和第二介电层上形成着衬垫层，以连接导电掩模层和沟道层。

    Source line formation in 3D vertical channel and memory
    16.
    发明授权
    Source line formation in 3D vertical channel and memory 有权
    三维垂直通道和存储器中的源极线形成

    公开(公告)号：US09362302B1

    公开(公告)日：2016-06-07

    申请号：US14608053

    申请日：2015-01-28

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Erh-Kun Lai

    IPC: G11C16/04 ,  H01L27/115 ,  G11C16/28 ,  H01L29/06 ,  H01L29/45 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/28

    CPC classification number: H01L27/11582 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/28 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/32133 ,  H01L27/1157 ,  H01L29/0642 ,  H01L29/0688 ,  H01L29/456 ,  H01L29/66833 ,  H01L29/7926

    Abstract: A memory device includes a plurality of stacks of conductive strips separated by insulating material, including at least a bottom level of conductive strips, a plurality of intermediate levels of conductive strips, and a top level of conductive strips. A reference conductor is disposed in a level between the bottom level of conductive strips and a substrate, isolated from the substrate by a layer of insulating material, and isolated from the bottom level by another layer of insulating material. A plurality of vertical active strips is disposed between the plurality of stacks in electrical contact with the substrate, and with the reference conductor. Charge storage structures are disposed in interface regions at cross-points between side surfaces of the conductive strips in the plurality of intermediate levels and the vertical active strips. A bias circuit is configured to provide different bias arrangements to the reference conductor and the substrate.

    Abstract translation: 存储器件包括由绝缘材料隔开的多个导体条叠层，包括至少底层的导电条，多个中间层的导电条和顶层的导电条。 参考导体设置在导电条的底层与衬底之间的层中，衬底通过绝缘材料层与衬底隔离，并通过另一层绝缘材料与底层隔离。 多个垂直活动条被设置在与基板电接触的多个堆叠之间以及与参考导体之间。 电荷存储结构设置在多个中间层中的导电条的侧表面与垂直活动条之间的交叉点的界面区域中。 偏置电路被配置为向参考导体和衬底提供不同的偏置布置。

    Method for fabricating memory device
    17.
    发明授权
    Method for fabricating memory device 有权
    制造存储器件的方法

    公开(公告)号：US09324731B1

    公开(公告)日：2016-04-26

    申请号：US14609581

    申请日：2015-01-30

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Erh-Kun Lai

    IPC: H01L21/336 ,  H01L29/792 ,  H01L21/70 ,  H01L27/115 ,  H01L21/28 ,  H01L21/311 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/02

    CPC classification number: H01L27/11582 ,  H01L21/02118 ,  H01L21/02532 ,  H01L21/28282 ,  H01L21/3086 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/11565 ,  H01L29/7926

    Abstract: A method for fabricating a memory device is provided: A multi-layer stack is formed on a substrate. The multi-layer stack is then patterned to form plural trenches extending along a first direction to define plural ridge-shaped stacks each of which comprises at least one conductive strip. Next, a memory layer and a channel layer are formed in sequence on bottoms and sidewalls of the trenches. A sacrifice layer is formed to fulfill the trenches. Subsequently, portions of the sacrifice layer, the memory layer and the channel layer formed in the trenches are removed to form plural openings exposing a portion of the substrate therefrom. After removing the remaining sacrifice layer, portions of the memory layer and the channel layer formed on the ridge-shaped stacks are patterned to form an interconnection between two adjacent trenches through two of the openings formed in the two adjacent trenches.

    Abstract translation: 提供了一种用于制造存储器件的方法：在衬底上形成多层堆叠。 然后将多层堆叠图案化以形成沿着第一方向延伸的多个沟槽，以限定多个脊形堆叠，每个堆叠层包括至少一个导电条。 接下来，在沟槽的底部和侧壁上依次形成存储层和沟道层。 形成牺牲层以实现沟槽。 随后，去除形成在沟槽中的牺牲层，存储层和沟道层的部分，以形成暴露基板的一部分的多个开口。 在去除剩余的牺牲层之后，将形成在脊形叠层上的存储层和沟道层的部分图案化以通过形成在两个相邻沟槽中的两个开口在两个相邻的沟槽之间形成互连。

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