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    INTEGRATED CIRCUITS WITH CONTEMPORANEOUSLY FORMED ARRAY ELECTRODES AND LOGIC INTERCONNECTS
    11.
    发明申请
    INTEGRATED CIRCUITS WITH CONTEMPORANEOUSLY FORMED ARRAY ELECTRODES AND LOGIC INTERCONNECTS 审中-公开
    集成电路与正在形成的阵列电极和逻辑互连

    公开(公告)号：US20070029630A1

    公开(公告)日：2007-02-08

    申请号：US11535873

    申请日：2006-09-27

    Applicant: Mirmajid Seyyedy ,  Glen Hush ,  Mark Tuttle ,  Terry Vollman

    Inventor： Mirmajid Seyyedy ,  Glen Hush ,  Mark Tuttle ,  Terry Vollman

    IPC: H01L43/00 ,  H01L23/52 ,  H01L29/76 ,  H01L29/94

    CPC classification number: H01L27/228 ,  G11C5/06 ,  G11C11/14 ,  H01L27/105 ,  H01L27/10882 ,  H01L27/10897

    Abstract: The invention relates to interconnects for an integrated circuit memory device. Embodiments of the invention include processes to fabricate interconnects for memory devices in relatively few steps. Embodiments of the invention further include memory devices with metallization layers having unequal pitch dimensions in different areas of the chip, thereby permitting simultaneous fabrication of array electrodes and electrical interconnects in different areas of the chip. This reduces the number of fabrication steps used to make interconnects, thereby speeding up fabrication and reducing production costs.

    Abstract translation: 本发明涉及用于集成电路存储器件的互连。 本发明的实施例包括以相对较少的步骤制造用于存储器件的互连的工艺。 本发明的实施例还包括具有在芯片的不同区域中具有不等间距尺寸的金属化层的存储器件，从而允许在芯片的不同区域中同时制造阵列电极和电互连。 这减少了用于制造互连的制造步骤的数量，从而加快制造并降低生产成本。

    System for testing semiconductor components
    12.
    发明申请
    System for testing semiconductor components 有权
    半导体元件测试系统

    公开(公告)号：US20070007987A1

    公开(公告)日：2007-01-11

    申请号：US11516342

    申请日：2006-09-06

    Applicant: Warren Farnworth ,  Mark Tuttle

    Inventor： Warren Farnworth ,  Mark Tuttle

    IPC: G01R31/26

    CPC classification number: G01R31/2886

    Abstract: A system for testing semiconductor components includes an interconnect, an alignment system for aligning a substrate to the interconnect, a bonding system for bonding the component to the interconnect, and a heating system for heating the component and the interconnect for separation. The interconnect includes interconnect contacts configured for bonding to, and then separation from component contacts on the components. The system can be utilized with a method that includes the steps of bonding the interconnect to the component to form bonded electrical connections, applying test signals through the bonded electrical connections, and then separating the interconnect from the component. The bonding step can be performed using metallurgical bonding, and the separating step can be performed using solder-wettable and solder non-wettable metal layers on the interconnect or the component. During the separating step the solder-wettable layers are dissolved, reducing adhesion of the bonded electrical connections, and permitting separation of the component and interconnect.

    Abstract translation: 用于测试半导体部件的系统包括互连，用于将衬底对准互连的对准系统，用于将部件接合到互连的接合系统，以及用于加热组件和用于分离的互连的加热系统。 互连包括被配置用于结合到组件上并且然后与组件上的组件触点分离的互连触点。 该系统可以利用包括以下步骤的方法：将互连件连接到部件以形成结合的电连接，通过结合的电连接施加测试信号，然后将互连件与部件分离。 接合步骤可以使用冶金结合进行，并且分离步骤可以使用在互连或部件上的可焊接润湿和焊接不可润湿的金属层进行。 在分离步骤期间，可焊接润湿层被溶解，减少了粘合的电连接的粘合性，并允许部件和互连的分离。

    Interconnect for testing semiconductor components
    13.
    发明申请
    Interconnect for testing semiconductor components 有权
    互连用于测试半导体元件

    公开(公告)号：US20070001700A1

    公开(公告)日：2007-01-04

    申请号：US11516328

    申请日：2006-09-06

    Applicant: Warren Farnworth ,  Mark Tuttle

    Inventor： Warren Farnworth ,  Mark Tuttle

    IPC: G01R31/02

    CPC classification number: G01R31/2886

    Abstract: An interconnect for testing semiconductor components includes interconnect contacts configured for bonding to, and then separation from component contacts on the components. The interconnect can be utilized with a method that includes the steps of bonding the interconnect to the component to form bonded electrical connections, applying test signals through the bonded electrical connections, and then separating the interconnect from the component. The bonding step can be performed using metallurgical bonding, and the separating step can be performed using solder-wettable and solder non-wettable metal layers on the interconnect or the component. During the separating step the solder-wettable layers are dissolved, reducing adhesion of the bonded electrical connections, and permitting separation of the component and interconnect.

    Abstract translation: 用于测试半导体部件的互连件包括互连触点，其被配置用于与部件上的部件触点接合，然后分离。 互连可以利用包括以下步骤的方法：将互连件连接到部件以形成结合的电连接，通过结合的电连接施加测试信号，然后将互连与部件分离。 接合步骤可以使用冶金结合进行，并且分离步骤可以使用在互连或部件上的可焊接润湿和焊接不可润湿的金属层进行。 在分离步骤期间，可焊接润湿层被溶解，减少了粘合的电连接的粘合性，并允许部件和互连的分离。

    Integrated circuit including sensor to sense environmental data, and system for testing
    15.
    发明申请
    Integrated circuit including sensor to sense environmental data, and system for testing 有权
    集成电路包括感应环境数据的传感器，以及用于测试的系统

    公开(公告)号：US20060077704A1

    公开(公告)日：2006-04-13

    申请号：US11286918

    申请日：2005-11-23

    Applicant: Mark Tuttle ,  D. Durcan

    Inventor： Mark Tuttle ,  D. Durcan

    IPC: G11C11/00

    CPC classification number: G11C11/16 ,  G11C29/02 ,  G11C29/028 ,  G11C2029/5006

    Abstract: An integrated circuit includes operational circuitry; a sensor configured to sense an environmental parameter; and adjustment circuitry coupled to the sensor and to the operational circuitry and configured to affect the operational circuitry to at least partially counteract the effects of the environmental parameter. A method of testing an integrated circuit includes supporting a sensor in the integrated circuit and using the sensor to sense environmental data.

    Abstract translation: 集成电路包括操作电路; 被配置为感测环境参数的传感器; 以及耦合到所述传感器和所述操作电路并被配置为影响所述操作电路以至少部分抵消所述环境参数的影响的调节电路。 一种测试集成电路的方法包括在集成电路中支持传感器，并使用传感器来感测环境数据。

    Chip carrier with magnetic shielding
    19.
    发明授权
    Chip carrier with magnetic shielding 有权
    芯片载体带磁屏蔽

    公开(公告)号：US06559521B2

    公开(公告)日：2003-05-06

    申请号：US10115960

    申请日：2002-04-05

    Applicant: Mark Tuttle

    Inventor： Mark Tuttle

    IPC: H01L23552

    CPC classification number: H05K1/0233 ,  H01L23/552 ,  H01L23/585 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01025 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/3025 ,  H01L2224/0401

    Abstract: A method and apparatus which provide one or more electromagnetic shield layers for integrated circuit chips containing electromagnetic circuit elements are disclosed. The shield layers may be in contact with the integrated circuit chip, including magnetic memory structures such as MRAMs, or in a flip-chip carrier, or both. A printed circuit board which supports the chip may also have one or more shield layers.

    Abstract translation: 公开了一种为包含电磁电路元件的集成电路芯片提供一个或多个电磁屏蔽层的方法和装置。 屏蔽层可以与集成电路芯片接触，包括诸如MRAM的磁存储器结构，或者在倒装芯片载体中，或者两者。 支撑芯片的印刷电路板也可以具有一个或多个屏蔽层。

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