公开(公告)号：US20110222817A1

公开(公告)日：2011-09-15

申请号：US13123317

申请日：2009-10-06

申请人： Ingo Smaglinski ,  Thomas Petigk ,  Martin Popp ,  Samuel Brantzen ,  Thomas Paatzsch

发明人： Ingo Smaglinski ,  Thomas Petigk ,  Martin Popp ,  Samuel Brantzen ,  Thomas Paatzsch

IPC分类号： G02B6/35

CPC分类号： G02B6/4215 ,  G02B6/29365 ,  G02B6/4214

摘要： The present invention relates to a multiplexer/demultiplexer with a connection for inputting and/or outputting an optical signal which has signal components of different wavelengths, a carrier plate (8) with at least one wavelength-sensitive element (11), a focussing member (13) with at least two focussing elements (14, 14′) as well as a detector or signal-generator plate (1), on which at least two detectors (4) or signal generators are arranged. To achieve this, it is proposed according to the invention that the focussing member (13) has at least one fibre stop, preferably formed integrally with the focussing member for adjusting a waveguide, and is connected to the detector or signal-generator plate (1) or to the carrier plate (8) via an elastic connecting element (23).

摘要翻译： 本发明涉及具有用于输入和/或输出具有不同波长的信号分量的光信号的连接的多路复用器/解复用器，具有至少一个波长敏感元件（11）的载板（8），聚焦部件 （13）具有至少两个聚焦元件（14,14'）以及检测器或信号发生器板（1），其上布置有至少两个检测器（4）或信号发生器。 为了实现这一点，根据本发明提出，聚焦构件（13）具有至少一个光纤停止件，优选地与用于调节波导的聚焦构件整体形成，并且连接到检测器或信号发生器板（1） ）或通过弹性连接元件（23）连接到承载板（8）。

公开(公告)号：US20090302380A1

公开(公告)日：2009-12-10

申请号：US12134740

申请日：2008-06-06

申请人： Werner Graf ,  Lars Heineck ,  Martin Popp

发明人： Werner Graf ,  Lars Heineck ,  Martin Popp

IPC分类号： H01L27/105 ,  H01L21/762

CPC分类号： H01L21/76232 ,  H01L21/743 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10891

摘要： In one embodiment, a memory cell includes a bit line arranged in a semiconductor substrate and a bit line contact region arranged adjacent the bit line. A word line is arranged above the bit line contact region in a trench formed in the semiconductor substrate. A generally U-shaped insulating layer is arranged in a bottom region of the trench and separates the bit line and the bit line contact region from the word line.

摘要翻译： 在一个实施例中，存储单元包括布置在半导体衬底中的位线和布置在位线附近的位线接触区域。 在形成在半导体衬底中的沟槽中的位线接触区域上方布置字线。 大致U形绝缘层布置在沟槽的底部区域中，并将位线和位线接触区域与字线分离。

公开(公告)号：US20080061340A1

公开(公告)日：2008-03-13

申请号：US11470792

申请日：2006-09-07

申请人： Lars Heineck ,  Martin Popp

发明人： Lars Heineck ,  Martin Popp

IPC分类号： H01L29/94

CPC分类号： H01L29/945 ,  H01L27/0207 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/10867 ,  H01L27/10876 ,  H01L27/10882 ,  H01L27/10891

摘要： A memory cell array having a plurality of memory cells is disclosed. In one embodiment, each memory cell includes a storage capacitor and an access transistor, a plurality of bit lines orientated in a first direction, a plurality of word lines orientated in a second direction, the second direction being perpendicular to the first direction, a semiconductor substrate with a surface, a plurality of active areas being formed in the semiconductor substrate, each active area extending in the second direction, the access transistors being partially formed in the active areas and electrically coupling corresponding ones of the storage capacitors to corresponding bit lines, wherein a gate electrode of each of the access transistors is connected with a corresponding word line, a capacitor dielectric of the storage capacitor has a relative dielectric constant of more than 8, and the word lines are disposed above the bit lines.

摘要翻译： 公开了一种具有多个存储单元的存储单元阵列。 在一个实施例中，每个存储单元包括存储电容器和存取晶体管，沿第一方向定向的多个位线，沿第二方向定向的多个字线，第二方向垂直于第一方向，半导体 具有表面的衬底，在半导体衬底中形成多个有源区域，每个有源区域在第二方向上延伸，存取晶体管部分地形成在有源区域中，并将对应的存储电容器电耦合到对应的位线， 其中每个存取晶体管的栅电极与对应的字线连接，所述存储电容器的电容电介质具有大于8的相对介电常数，并且所述字线位于所述位线之上。

公开(公告)号：US20060060734A1

公开(公告)日：2006-03-23

申请号：US10534341

申请日：2002-11-11

申请人： Martin Popp ,  Ingo Smaglinski ,  Jens Haase ,  Gerhard Himmelsbach

发明人： Martin Popp ,  Ingo Smaglinski ,  Jens Haase ,  Gerhard Himmelsbach

IPC分类号： E04G3/00

CPC分类号： G02B7/006 ,  G02B6/29367 ,  G02B6/32 ,  G02B6/3636 ,  G02B6/3652 ,  G02B6/3696 ,  G02B6/4214

摘要： The invention relates to a support element (1), for mounting at least two wave-modifying elements, with support of services, arranged parallel to each other. According to the invention, support element for mounting at least two wave-modifying elements and corresponding production method maybe achieved, whereby the support surfaces each have at least one opening and the openings are connected to each other by means of at least one through drilling.

摘要翻译： 本发明涉及一种支撑元件（1），用于安装至少两个波形修改元件，其具有彼此平行布置的服务支撑。 根据本发明，可以实现用于安装至少两个波浪修改元件的支撑元件和相应的制造方法，由此支撑表面各自具有至少一个开口，并且开口通过至少一个穿孔相互连接。

公开(公告)号：US06956260B2

公开(公告)日：2005-10-18

申请号：US10463019

申请日：2003-06-17

申请人： Dirk Manger ,  Till Schlösser ,  Martin Popp ,  Michael Sesterhenn

发明人： Dirk Manger ,  Till Schlösser ,  Martin Popp ,  Michael Sesterhenn

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L27/10876 ,  H01L27/10891

摘要： In semiconductor memories, in particular DRAMs, the memory cells of which have vertical transistors at vertical lands formed from substrate material, gate electrodes are formed as spacers which run around the land. The gate electrodes of adjacent memory cells conventionally have to be retroactively connected to form word lines. It is known to fill spaces between adjacent lands with an oxide, with the result that the spacers are formed directly as word lines but only cover two side walls of a land. Two transistors which are connected in parallel are formed at these side walls instead of a single transistor, since the gate electrode does not run around the land. The invention proposes a method for fabricating a semiconductor memory in which all four side walls of a land are covered by the word lines and at the same time lands of adjacent memory cells are connected to one another by the word lines.

摘要翻译： 在半导体存储器中，特别是DRAM，其存储单元在由衬底材料形成的垂直焊盘处具有垂直晶体管，栅电极形成为围绕焊盘运行的间隔件。 相邻存储单元的栅电极通常必须追溯地连接以形成字线。 已知用相邻的焊盘之间的空间填充氧化物，结果是间隔件直接形成为字线，而仅覆盖焊盘的两个侧壁。 并联连接的两个晶体管形成在这些侧壁而不是单个晶体管，因为栅电极不会绕着焊盘运行。 本发明提出一种半导体存储器的制造方法，其中，由字线覆盖焊盘的四个侧壁，同时通过字线将相邻存储单元的焊盘相互连接。

公开(公告)号：US06835666B2

公开(公告)日：2004-12-28

申请号：US10291070

申请日：2002-11-08

申请人： Martin Popp

发明人： Martin Popp

IPC分类号： H01L21302

CPC分类号： H01L21/3086

摘要： A mask is fabricated by applying a sacrificial layer on a semiconductor wafer. The sacrificial layer is then processed with the aid of a first and a second lithographic process sequence in order to pattern the sacrificial layer in a first and a second direction. A hard mask layer is subsequently applied in order to completely enclose the patterned sacrificial layer. Finally, the sacrificial layer is then removed from the hard mask layer.

摘要翻译： 通过在半导体晶片上施加牺牲层来制造掩模。 然后借助于第一和第二光刻工艺顺序处理牺牲层，以便沿第一和第二方向图案化牺牲层。 随后施加硬掩模层以完全包围图案化的牺牲层。 最后，从硬掩模层去除牺牲层。

公开(公告)号：US20130187031A1

公开(公告)日：2013-07-25

申请号：US13355814

申请日：2012-01-23

申请人： Martin Popp ,  Beat De Coi

发明人： Martin Popp ,  Beat De Coi

IPC分类号： H01J40/14 ,  H01L31/18 ,  B82Y20/00

CPC分类号： G01S17/36 ,  G01S7/4863 ,  G01S17/89

摘要： A sensor apparatus including at least one analog and one digital circuit component and an analog/digital converter for converting analog signals of the analog circuit component into digital signals for the digital circuit component, and vice versa, wherein the analog circuit component and the digital circuit components include at least one module for electronically implementing a function, and wherein one of the modules of the analog circuit component is embodied as a sensor device for detecting optical radiation and one of the modules of the digital circuit component is embodied as a signal processing device for processing digital signals. In order to enable improved integration into application-based sensor devices, the circuit components including the analog/digital converter are integrated as an integrated circuit in a chip and the chip is manufactured as a semiconductor structure using 1-poly technology.

摘要翻译： 一种传感器装置，包括至少一个模拟和一个数字电路部件和用于将模拟电路部件的模拟信号转换为数字电路部件的数字信号的模/数转换器，反之亦然，其中模拟电路部件和数字电路 组件包括用于电子地实现功能的至少一个模块，并且其中模拟电路部件的模块之一被实现为用于检测光辐射的传感器装置，并且数字电路部件的模块之一被实现为信号处理装置 用于处理数字信号。 为了能够改进集成到基于应用的传感器装置中，包括模拟/数字转换器的电路部件作为集成电路集成在芯片中，并且该芯片被制造为使用1-聚技术的半导体结构。

公开(公告)号：US20100097835A1

公开(公告)日：2010-04-22

申请号：US12252826

申请日：2008-10-16

申请人： Martin Popp ,  Till Schloesser

发明人： Martin Popp ,  Till Schloesser

IPC分类号： G11C5/06 ,  G11C11/24

CPC分类号： G11C5/063 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891

摘要： An integrated circuit including a memory cell array comprises active area lines, bitlines, the bitlines being arranged so that an individual one intersects a plurality of the active area lines to form bitline-contacts, respectively, the bitlines being arranged at a bitline pitch, wordlines being arranged so that an individual one of the wordlines intersects a plurality of the active area lines, and an individual one of the wordlines intersects a plurality of the bitlines, the wordlines being arranged at a wordline pitch, wherein neighboring bitline-contacts, each of which is connected to one of the active area lines, are connected with different bitlines, and the bitline pitch is different from the wordline pitch.

摘要翻译： 包括存储单元阵列的集成电路包括有源区线，位线，所述位线被布置成使得单独的位线与多个有源区域线相交以分别形成位线接触，位线布置在位线间距处，字线 被布置为使得单个字线中的单个字符与多个有效区域线相交，并且字线中的单个字符与多个位线相交，字线以字线间距排列，其中相邻位线接触，每个 连接到有源区线之一，与不同的位线连接，位线间距与字线间距不同。

公开(公告)号：US20100096669A1

公开(公告)日：2010-04-22

申请号：US12252853

申请日：2008-10-16

申请人： Martin Popp ,  Till Schloesser

发明人： Martin Popp ,  Till Schloesser

IPC分类号： H01L29/76 ,  H01L27/108

CPC分类号： H01L27/10885 ,  H01L27/10882 ,  H01L27/10888 ,  H01L27/10891

摘要： An integrated circuit including a memory cell array comprises transistors being arranged along parallel active area lines, bitlines, the bitlines being arranged so that an individual one intersects a plurality of the active area lines to form bitline-contacts, respectively, the bitlines being formed as wiggled lines, wordlines being arranged so that an individual one of the wordlines intersects a plurality of the active area lines, and an individual one of the wordlines intersects a plurality of the bitlines, wherein neighboring bitline-contacts, each of which is connected to one of the active area lines, are connected with different bitlines.

摘要翻译： 包括存储单元阵列的集成电路包括沿着并行有源区域线，位线布置的晶体管，位线被布置成使得各个相互交叉的多个有源区域线分别形成位线接触，位线形成为 摆动的线条，字线被布置成使得字线中的单个字符与多个有效区域线相交，并且字线中的单个字符与多个位线相交，其中相邻的位线接触，其中每一个连接到一个 的有源面积线与不同的位线连接。

公开(公告)号：US07700983B2

公开(公告)日：2010-04-20

申请号：US11300853

申请日：2005-12-15

申请人： Martin Popp ,  Juergen Faul ,  Thomas Schuster ,  Jens Hahn

发明人： Martin Popp ,  Juergen Faul ,  Thomas Schuster ,  Jens Hahn

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L27/10894 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/785

摘要： One embodiment of the present invention relates to a transistor that is at least partially formed in a semiconductor substrate having a surface. In particular, the transistor includes a first source/drain region, a second source/drain region, a channel region connecting said first and second source/drain regions. Said channel region is disposed in said semiconductor substrate. A channel direction is defined by a line connecting said first and said second source/drain regions. A gate groove is formed in said semiconductor substrate. Said gate groove is formed adjacent to said channel region. Said gate groove includes an upper portion and a lower portion, said upper portion being adjacent to said lower portion, and a gate dielectric layer disposed between said channel region and said gate groove. The lower portion of said gate groove is filled with polysilicon whereas the upper portion of said gate groove is filled with a metal or a metal compound thereby forming a gate electrode disposed along said channel region. Said gate electrode controls an electrical current flowing between said first and second source/drain regions.

摘要翻译： 本发明的一个实施例涉及至少部分地形成在具有表面的半导体衬底中的晶体管。 特别地，晶体管包括第一源极/漏极区域，第二源极/漏极区域，连接所述第一和第二源极/漏极区域的沟道区域。 所述沟道区设置在所述半导体衬底中。 通道方向由连接所述第一和第二源极/漏极区域的线限定。 在所述半导体衬底中形成栅极沟槽。 所述栅极槽与所述沟道区相邻地形成。 所述栅极槽包括上部和下部，所述上部与所述下部相邻，并且栅介质层设置在所述沟道区和所述栅沟之间。 所述栅极沟槽的下部填充有多晶硅，而所述栅极沟槽的上部填充有金属或金属化合物，从而形成沿所述沟道区域设置的栅电极。 所述栅电极控制在所述第一和第二源/漏区之间流动的电流。