公开(公告)号：US07151293B1

公开(公告)日：2006-12-19

申请号：US10928582

申请日：2004-08-27

申请人： Hidehiko Shiraiwa ,  Jaeyong Park ,  Satoshi Torii ,  Hideki Arakawa ,  Masaru Yano

发明人： Hidehiko Shiraiwa ,  Jaeyong Park ,  Satoshi Torii ,  Hideki Arakawa ,  Masaru Yano

IPC分类号： H01L29/72

CPC分类号： H01L29/792 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833

摘要： A SONOS memory cell, formed within a semiconductor substrate, includes a bottom dielectric disposed on the semiconductor substrate, a charge trapping material disposed on the bottom dielectric, and a top dielectric disposed on the charge trapping material. Furthermore, the SONOS memory cell includes a word-line gate structure disposed on the top dielectric and at least one bit-line gate for inducing at least one inversion bit-line within the semiconductor substrate.

公开(公告)号：US20110310666A1

公开(公告)日：2011-12-22

申请号：US13203612

申请日：2009-04-30

申请人： Takashi Miida ,  Riichiro Shirota ,  Hideki Arakawa ,  Ching Sung Yang ,  Tzung Ling Lin

发明人： Takashi Miida ,  Riichiro Shirota ,  Hideki Arakawa ,  Ching Sung Yang ,  Tzung Ling Lin

IPC分类号： G11C16/10

CPC分类号： G11C16/3427 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/102 ,  G11C16/3418 ,  H01L27/11524 ,  H01L27/11526

摘要： In a programming method for a NAND flash memory device, a self-boosting scheme is used to eliminate excess electrons in the channel of an inhibit cell string that would otherwise cause programming disturb. The elimination is enabled by applying a negative voltage to word lines connected to the inhibit cell string before boosting the channel, and this leads to bringing high program immunity. A row decoder circuitry to achieve the programming operation and a file system architecture based on the programming scheme to improve the efficiency of file management are also described.

摘要翻译： 在NAND闪速存储器件的编程方法中，使用自增强方案来消除否则会导致编程干扰的抑制单元串的通道中的多余电子。 在增强通道之前，通过对连接到禁止单元串的字线施加负电压来实现消除，并且这导致高程序抗扰性。 还描述了实现编程操作的行解码器电路和基于编程方案的文件系统架构以提高文件管理的效率。

公开(公告)号：US07903470B2

公开(公告)日：2011-03-08

申请号：US12335189

申请日：2008-12-15

申请人： Te-Chang Tseng ,  Chun-Yi Tu ,  Hideki Arakawa ,  Yamasaki Kyoji

发明人： Te-Chang Tseng ,  Chun-Yi Tu ,  Hideki Arakawa ,  Yamasaki Kyoji

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： G11C16/16

摘要： An integrated circuit is provided. The integrated circuit includes a memory device and a discharge circuit. The discharge circuit discharges the well voltage line and the first voltage line of the memory device after the end of the erasing period and includes a first and second switch circuit and a first and second control voltage supplier. The first switch circuit is coupled between the well voltage line, the first voltage line and a second supplier. The second switch circuit is coupled between the first switch circuit and a reference voltage. The first control voltage supplier is coupled to the first switch circuit and supplies a first control voltage to turn on the first switch circuit during a first discharge period. The second control voltage supplier is coupled to the second switch circuit, and supplies a second control voltage to turn on the second switch circuit during a second discharge period.

摘要翻译： 提供集成电路。 集成电路包括存储器件和放电电路。 放电电路在擦除周期结束后对存储器件的阱电压线和第一电压线放电，并且包括第一和第二开关电路以及第一和第二控制电压供应器。 第一开关电路耦合在阱电压线，第一电压线和第二供电器之间。 第二开关电路耦合在第一开关电路和参考电压之间。 第一控制电压供应器耦合到第一开关电路，并且在第一放电期间提供第一控制电压以接通第一开关电路。 第二控制电压供应器耦合到第二开关电路，并且在第二放电周期期间提供第二控制电压以接通第二开关电路。

公开(公告)号：US20090161426A1

公开(公告)日：2009-06-25

申请号：US12335784

申请日：2008-12-16

申请人： Chun-Yi TU ,  Te-Chang Tseng ,  Hideki Arakawa ,  Takeshi Nakayama

发明人： Chun-Yi TU ,  Te-Chang Tseng ,  Hideki Arakawa ,  Takeshi Nakayama

IPC分类号： G11C16/04

CPC分类号： G11C16/10

摘要： A memory programming method is provided. A first programming operation is performed to program a multi level cell from an initial state to a first target state, which corresponds to a storage data and has a first threshold voltage range. A flag bit of the NAND flash is set to a first state to indicate that the first programming operation has been performed. A second programming operation is performed to program the multi level cell from the first target state to a second target state, which corresponds to the storage data and has a second threshold voltage range. The flag bit is set to a second state to indicate that the second programming operation has been performed.

摘要翻译： 提供了存储器编程方法。 执行第一编程操作以将多级单元从初始状态编程到对应于存储数据的第一目标状态，并具有第一阈值电压范围。 NAND闪存的标志位被设置为第一状态以指示已经执行了第一编程操作。 执行第二编程操作以将多级单元从第一目标状态编程为对应于存储数据并具有第二阈值电压范围的第二目标状态。 标志位被设置为第二状态以指示已经执行了第二编程操作。

公开(公告)号：US20070076492A1

公开(公告)日：2007-04-05

申请号：US11529790

申请日：2006-09-29

申请人： Hideki Arakawa ,  Satoru Kawamoto

发明人： Hideki Arakawa ,  Satoru Kawamoto

IPC分类号： G11C7/00

CPC分类号： G11C5/145

摘要： A storage device and its control method are described, according to which a bias voltage to be supplied to a memory cell array is selected from boosted voltages which are increased from an external voltage and non-boosted voltages which are not increased from the external voltage. In the period during which a DC-DC converter section supplies a boosted voltage increased from the external voltage to an internal bias line for supplying a bias voltage to the memory cell array, a non-boosted voltage supply section for supplying a non-boosted voltage equal to or less than the external voltage is in its inactive state. In the period during which the non-boosted voltage supply section supplies a non-boosted voltage to the internal bias line, the DC-DC converter section is in its inactive state. In the period during which a boosted voltage is supplied to the internal bias line, the DC-DC converter section is used for ensuring sufficient power supply ability, and in the period during which the non-boosted voltage is supplied to the internal bias line, the DC-DC converter section can be kept in its inactive state. Thus, the power consumed by the DC-DC converter section can be saved in the period during which the supply of a boosted voltage is unnecessary.

摘要翻译： 描述了存储装置及其控制方法，根据该存储装置及其控制方法，从提供给存储单元阵列的偏置电压从从外部电压增加的升压电压和不从外部电压增加的非升压电压中选择。 在DC-DC转换器部分将从外部电压增加的升压电压提供给用于向存储单元阵列提供偏置电压的内部偏置线的期间内，提供非升压电压 等于或小于外部电压处于其无效状态。 在非升压电压供给部向内部偏置线供给非升压电压的期间，DC-DC转换部处于非活动状态。 在向内部偏置线提供升压电压的期间，DC-DC转换部用于确保充分的供电能力，在向内部偏置线供给非升压电压的期间中， DC-DC转换器部分可以保持在其非活动状态。 因此，在不需要提供升压电压的期间，可以节省DC-DC转换器部分消耗的功率。

公开(公告)号：US5590073A

公开(公告)日：1996-12-31

申请号：US345695

申请日：1994-11-21

申请人： Hideki Arakawa ,  Takashi Narikiyo

发明人： Hideki Arakawa ,  Takashi Narikiyo

IPC分类号： G11C7/10 ,  G11C14/00 ,  G11C16/02 ,  G11C17/00 ,  G11C11/34

CPC分类号： G11C7/1078 ,  G11C14/00 ,  G11C7/1051

摘要： A semiconductor nonvolatile memory device including first and second bit lines, a buffer memory connected to the first and second bit lines, an electrically erasable programmable nonvolatile memory connected to the first and second bit lines, a writing latch circuit to which the first and second bit lines are connected in parallel and having a differential sensor type sense amplifier, and a switching circuit for switching the nonvolatile memory and the latch circuit to a nonconnected state at the time of operation of the buffer memory and switching the buffer memory and the latch circuit to a nonconnected state at the time of a writing or erasure operation on the nonvolatile memory.

摘要翻译： 一种包括第一和第二位线的半导体非易失性存储器件，连接到第一和第二位线的缓冲存储器，连接到第一和第二位线的电可擦除可编程非易失性存储器，写入锁存电路，第一和第二位 线并联并具有差分传感器型读出放大器，以及用于在缓冲存储器操作时将非易失性存储器和锁存电路切换到非连接状态并将缓冲存储器和锁存电路切换到 在非易失性存储器上的写入或擦除操作时的非连接状态。

公开(公告)号：US5459694A

公开(公告)日：1995-10-17

申请号：US219542

申请日：1994-03-29

申请人： Hideki Arakawa

发明人： Hideki Arakawa

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/28 ,  H01L21/8247 ,  H01L27/115 ,  G11C7/00

CPC分类号： G11C16/28

摘要： A semiconductor nonvolatile memory device which can adopt a folded bit line system and can achieve an enhancement of speed of the read out time etc., which device adopting a differential type sensing system comprising a bit line BL and an inverted bit line BL.sub.-- connected in parallel to a sense amplifier SA.sub.f, wherein provision is made of a first memory cell MC1 connected to a word line WL and the bit line BL; a second memory cell MC2 connected to the word line WL which is common also for the first memory cell MC1, and, connected to the inverted bit line BL.sub.-- ; and a circuit BVA which retains the potential of either one of bit lines of the bit line BL and the inverted bit line BL.sub.-- at the first potential at the time of a read out operation, and, sets the potential of the other bit line at the second potential made to have a difference from the first potential for a predetermined time.

摘要翻译： 一种半导体非易失性存储器件，其可以采用折叠位线系统并且可以实现读出时间速度等的提高，该器件采用包括连接在一起的位线BL和反相位线BL的差分型感测系统 平行于读出放大器SAf，其中提供连接到字线WL和位线BL的第一存储器单元MC1; 连接到第一存储单元MC1公用的字线WL的第二存储单元MC2，并连接到反相位线BL-; 以及在读出操作时将位线BL和反相位线BL-的位线中的任一个的电位保持为第一电位的电路BVA，并将另一位线的电位设置在 在预定时间内产生与第一电位不同的第二电位。

公开(公告)号：US4699690A

公开(公告)日：1987-10-13

申请号：US831499

申请日：1986-02-21

申请人： Hideki Arakawa

发明人： Hideki Arakawa

IPC分类号： H01L27/115 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  B44C1/22

CPC分类号： H01L29/66825 ,  H01L21/28132 ,  H01L21/28141 ,  H01L21/28273 ,  H01L27/11517 ,  H01L29/7883 ,  Y10S148/106 ,  Y10S148/114

摘要： A method of producing a semiconductor memory device comprises the steps of forming a first mask on a substrate and forming an opening in the first mask, implanting impurity ions into the substrate from the opening in the first mask so as to form an impurity region, forming a side wall layer of oxidation-resistant material having a predetermined width on a side surface of the opening in the first mask, forming a tunnel region having a width determined by the predetermined width by using the oxidation-resistant side wall layer as a second mask and forming a gate part on the tunnel region.

摘要翻译： 一种制造半导体存储器件的方法包括以下步骤：在衬底上形成第一掩模并在第一掩模中形成开口，从第一掩模中的开口将杂质离子注入到衬底中，以形成杂质区，形成 在第一掩模的开口的侧面上具有预定宽度的抗氧化材料的侧壁层，通过使用抗氧化侧壁层作为第二掩模形成具有由预定宽度确定的宽度的隧道区域 以及在隧道区域上形成栅极部分。

公开(公告)号：US4368524A

公开(公告)日：1983-01-11

申请号：US170175

申请日：1980-07-18

申请人： Kazuhisa Nakamura ,  Hideki Arakawa

发明人： Kazuhisa Nakamura ,  Hideki Arakawa

IPC分类号： H01L27/112 ,  G05F3/20 ,  G11C16/06 ,  G11C16/30 ,  G11C17/00 ,  H01L21/761 ,  H01L21/822 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/04 ,  H01L27/105 ,  H01L27/12 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

CPC分类号： G11C16/30 ,  G05F3/205 ,  H01L21/761 ,  H01L27/105 ,  H01L27/12 ,  H01L29/78 ,  H01L29/792

摘要： A semiconductor device for comprising electrically alterable read-only memories formed in and on the same silicon substrate is disclosed. The read-only memories are driven by both a first voltage having one polarity and a second voltage having the opposite polarity. The first voltage is supplied from an external unipolar voltage source, but the second voltage is generated by a bipolar voltage generator which is located on the same silicon substrate and is driven by said external unipolar voltage source.

摘要翻译： 公开了一种半导体器件，其包括形成在同一硅衬底上和之上的电可更改的只读存储器。 只读存储器由具有一个极性的第一电压和具有相反极性的第二电压驱动。 第一电压由外部单极性电压源提供，但是第二电压由双极性电压发生器产生，该双极性电压发生器位于同一硅衬底上并由所述外部单极性电压源驱动。

公开(公告)号：US4298629A

公开(公告)日：1981-11-03

申请号：US128172

申请日：1980-03-07

申请人： Takao Nozaki ,  Takashi Ito ,  Hideki Arakawa ,  Hajime Ishikawa ,  Masaichi Shinoda

发明人： Takao Nozaki ,  Takashi Ito ,  Hideki Arakawa ,  Hajime Ishikawa ,  Masaichi Shinoda

IPC分类号： H01L29/78 ,  C01B21/068 ,  H01L21/318 ,  C23C11/00

CPC分类号： H01L21/3185 ,  H01L21/318

摘要： In a method for forming an insulating film on a semiconductor substrate surface, the silicon nitride of the insulating film has been formed by a plasma CVD or a direct nitridation. In the present invention, a gas plasma of a nitrogen-containing gas is generated in a direct nitridation reaction chamber, and the semiconductor silicon body is heated to a temperature of from approximately 800 to approximately 1300.degree. C. within the gas plasma atmosphere, thereby forming the silicon nitride film. The resulting silicon nitride film has a dense structure and a low oxygen concentration and a thick silicon nitride film is formed in a short period by direct nitridation of silicon.

摘要翻译： 在半导体衬底表面上形成绝缘膜的方法中，绝缘膜的氮化硅通过等离子体CVD或直接氮化形成。 在本发明中，在直接氮化反应室中产生含氮气体的气体等离子体，在气体等离子体气氛中将半导体硅体加热至约800〜约1300℃的温度，由此 形成氮化硅膜。 所得到的氮化硅膜具有致密结构和低氧浓度，并且通过硅的直接氮化在短时间内形成厚的氮化硅膜。