公开(公告)号：US07405147B2

公开(公告)日：2008-07-29

申请号：US10707996

申请日：2004-01-30

申请人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

发明人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

IPC分类号： H01L21/00

CPC分类号： B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： A method for manufacturing a structure includes providing a structure having an insulator layer with at least one interconnect and forming a sub lithographic template mask on the insulator layer. A selective etching step is used for etching the insulator layer through the sub lithographic template mask to form sub lithographic features near the at least one interconnect. A supra lithographic blocking mask may also be utilized. In another aspect, the method includes forming pinch off sections of sub lithographic size formed in a capping layer on the insulator layer. A semiconductor structure includes an insulator layer having at least one interconnect feature and at least one column formed in the insulator layer. A plurality of sub lithographic features formed on a top portion of the insulator layer and communicating with the at least one column is also provided. The plurality of sub lithographic features have a cross section or diameter less than any of the at least one column. A gap may be prohibited from forming on or near scribe lines or vias.

摘要翻译： 一种制造结构的方法包括提供具有至少一个互连的绝缘层的结构，并在绝缘体层上形成次光刻模板掩模。 选择性蚀刻步骤用于通过子光刻模板掩模蚀刻绝缘体层，以在至少一个互连附近形成亚光刻特征。 还可以使用超光刻阻挡掩模。 另一方面，该方法包括形成在绝缘体层上的覆盖层中形成的亚光刻尺寸的夹断部分。 半导体结构包括具有至少一个互连特征的绝缘体层和形成在绝缘体层中的至少一个列。 还提供了形成在绝缘体层的顶部并与至少一个柱连通的多个次级光刻特征。 所述多个亚光刻特征具有小于或小于所述至少一列中的任何一个的横截面或直径。 可能禁止在划线或通孔上或附近形成间隙。

公开(公告)号：US20060258159A1

公开(公告)日：2006-11-16

申请号：US11130078

申请日：2005-05-16

申请人： Matthew Colburn ,  Ricardo Donaton ,  Conal Murray ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Theodorus Eduardus Fransiscus Standaert ,  Xiao Liu

发明人： Matthew Colburn ,  Ricardo Donaton ,  Conal Murray ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Theodorus Eduardus Fransiscus Standaert ,  Xiao Liu

IPC分类号： H01B13/00 ,  H01L21/302 ,  B44C1/22

CPC分类号： H01L21/32139 ,  H01L21/0271 ,  H01L21/31144 ,  H01L21/7682

摘要： A process for preparing an electronics structure involves coating a substrate stack with a sacrificial multilayer hardmask stack, developing a pattern in a resist layer coated on a topmost layer of the multilayer hardmask stack, transferring the pattern into the hardmask stack, blocking a portion of the pattern, and then transferring an unblocked portion of the pattern into the substrate stack. Electronics structures prepared with the process are useful to prepare electronics devices, such as computers and the like. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader quickly to ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the appended issued claims.

摘要翻译： 用于制备电子结构的方法包括用牺牲多层硬掩模堆叠涂覆衬底叠层，在涂覆在多层硬掩模堆叠的最上层上的抗蚀剂层中形成图案，将图案转移到硬掩模堆叠中，阻挡部分 图案，然后将图案的未封闭部分转印到基底叠层中。 使用该方法制备的电子结构对制备电子设备（例如计算机等）是有用的。 要强调的是，该摘要被提供以符合要求抽象的规则，这将允许搜索者或其他读者快速地确定技术公开的主题。 提交它的理解是，它不会用于解释或限制所附权利要求的范围或含义。

公开(公告)号：US07776737B2

公开(公告)日：2010-08-17

申请号：US12191534

申请日：2008-08-14

申请人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus Eduardus Standaert

发明人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus Eduardus Standaert

IPC分类号： H01L21/4763 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76816 ,  H01L21/76805 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit which includes a semiconductor substrate, a first metal wiring level on the semiconductor substrate which includes metal wiring lines, an interconnect wiring level on the first metal wiring level which includes a via interconnect within an interlevel dielectric, a second metal wiring level on the interconnect wiring level which includes metal wiring lines, at least one metal wiring line having a plurality of dielectric fill shapes that reduces the cross sectional area of the at least one metal wiring line, and wherein the via interconnect makes electrical contact between a metal line in the first wiring level and the at least one metal wiring line in the second wiring level, the via interconnect being adjacent to and spaced from the plurality of dielectric fill shapes. Also disclosed is a method in which a plurality of dielectric fill shapes are placed adjacent to and spaced from a via contact area in a wiring line in a second wiring level.

摘要翻译： 一种集成电路，其包括半导体衬底，所述半导体衬底上的包括金属布线的第一金属布线级别，所述第一金属布线层上的互连布线级别，其包括层间电介质内的通孔布线，第二金属布线级别 包括金属布线的互连布线层，至少一个具有多个介电填充形状的金属布线，其减小了所述至少一个金属布线的横截面积，并且其中所述通孔互连使金属线 在第一布线级别和第二布线级中的至少一个金属布线中，通孔布线与多个介质填充形状相邻并间隔开。 还公开了一种方法，其中多个介电填充形状被放置成与第二布线层中的布线中的通孔接触区域相邻并间隔开。

公开(公告)号：US08298948B2

公开(公告)日：2012-10-30

申请号：US12613551

申请日：2009-11-06

申请人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  David L. Rath ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus Eduardus Standaert ,  Chih-Chao Yang

发明人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  David L. Rath ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus Eduardus Standaert ,  Chih-Chao Yang

IPC分类号： H01L21/44 ,  H01L21/302

CPC分类号： H01L23/53238 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76865 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for capping lines includes forming a metal film layer on a copper line by a selective deposition process, the copper line disposed in a dielectric substrate, wherein the depositing also results in the deposition of stray metal material on the surface of the dielectric substrate, and etching with an isotropic etching process to remove a portion of the metal film layer and the stray metal material on the surface of the dielectric substrate, wherein the metal film layer is deposited at an initial thickness sufficient to leave a metal film layer cap remaining on the copper line following the removal of the stray metal material.

摘要翻译： 一种封盖线的方法包括通过选择性沉积工艺在铜线上形成金属膜层，铜线设置在电介质基底中，其中沉积还导致杂散金属材料沉积在介质基片的表面上， 并用各向同性蚀刻工艺进行蚀刻以除去电介质基底表面上的金属膜层和杂散金属材料的一部分，其中金属膜层以足以使金属膜层盖保持在其上的初始厚度沉积 铜线除去杂散金属材料。

公开(公告)号：US07488679B2

公开(公告)日：2009-02-10

申请号：US11461137

申请日：2006-07-31

申请人： Theodorus Eduardus Standaert ,  Pegeen M. Davis ,  John Anthony Fitzsimmons ,  Stephen Edward Greco ,  Tze-Man Ko ,  Naftali Eliahu Lustig ,  Lee Matthew Nicholson ,  Sujatha Sankaran

发明人： Theodorus Eduardus Standaert ,  Pegeen M. Davis ,  John Anthony Fitzsimmons ,  Stephen Edward Greco ,  Tze-Man Ko ,  Naftali Eliahu Lustig ,  Lee Matthew Nicholson ,  Sujatha Sankaran

IPC分类号： H01L21/4763 ,  H01L23/48

CPC分类号： H01L21/76808 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76846 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming an interconnect structure in an inter-layer dielectric (ILD) material, the method include the steps of creating one or more via openings in the ILD material; forming a first liner covering at least one of the one or more via openings; creating one or more trench openings on top of at least one of the one or more via openings covered by the first liner; and forming a second liner covering the trenching openings and at least part of the first liner. An interconnect structure formed by the method is also provided.

摘要翻译： 一种在层间电介质（ILD）材料中形成互连结构的方法，所述方法包括以下步骤：在ILD材料中形成一个或多个通路孔; 形成覆盖所述一个或多个通孔开口中的至少一个的第一衬垫; 在由所述第一衬垫覆盖的所述一个或多个通孔中的至少一个的顶部上形成一个或多个沟槽开口; 以及形成覆盖所述下料开口和所述第一衬里的至少一部分的第二衬里。 还提供了通过该方法形成的互连结构。

公开(公告)号：US07394154B2

公开(公告)日：2008-07-01

申请号：US11162513

申请日：2005-09-13

申请人： Paul S. McLaughlin ,  Sujatha Sankaran ,  Theodorus E. Standaert

发明人： Paul S. McLaughlin ,  Sujatha Sankaran ,  Theodorus E. Standaert

IPC分类号： H01L23/52

CPC分类号： H01L21/31144 ,  H01L21/3212 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/76885

摘要： A semiconductor interconnect structure and method providing an embedded barrier layer to prevent damage to the dielectric material during or after Chemical Mechanical Polishing. The method employs a combination of an embedded film, etchback, using either selective CoWP or a conformal cap such as a SiCNH film, to protect the dielectric material from the CMP process as well as subsequent etch, clean and deposition steps of the next interconnect level.

摘要翻译： 一种半导体互连结构和方法，提供嵌入的阻挡层，以防止在化学机械抛光期间或之后损坏电介质材料。 该方法采用嵌入膜，回蚀，使用选择性CoWP或诸如SiCNH膜的共形盖的组合来保护介电材料免受CMP工艺以及随后的下一个互连级别的蚀刻，清洁和沉积步骤 。

公开(公告)号：US20080026568A1

公开(公告)日：2008-01-31

申请号：US11461137

申请日：2006-07-31

申请人： Theodorus Eduardus Standaert ,  Pegeen M. Davis ,  John Anthony Fitzsimmons ,  Stephen Edward Greco ,  Tze-Man Ko ,  Naftali Eliahu Lustig ,  Lee Matthew Nicholson ,  Sujatha Sankaran

发明人： Theodorus Eduardus Standaert ,  Pegeen M. Davis ,  John Anthony Fitzsimmons ,  Stephen Edward Greco ,  Tze-Man Ko ,  Naftali Eliahu Lustig ,  Lee Matthew Nicholson ,  Sujatha Sankaran

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76846 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming an interconnect structure in an inter-layer dielectric (ILD) material, the method include the steps of creating one or more via openings in the ILD material; forming a first liner covering at least one of the one or more via openings; creating one or more trench openings on top of at least one of the one or more via openings covered by the first liner; and forming a second liner covering the trenching openings and at least part of the first liner. An interconnect structure formed by the method is also provided.

摘要翻译： 一种在层间电介质（ILD）材料中形成互连结构的方法，所述方法包括以下步骤：在ILD材料中形成一个或多个通路孔; 形成覆盖所述一个或多个通孔开口中的至少一个的第一衬垫; 在由所述第一衬垫覆盖的所述一个或多个通孔中的至少一个的顶部上形成一个或多个沟槽开口; 以及形成覆盖所述下料开口和所述第一衬里的至少一部分的第二衬里。 还提供了通过该方法形成的互连结构。

公开(公告)号：US20070232048A1

公开(公告)日：2007-10-04

申请号：US11395962

申请日：2006-03-31

申请人： Koji Miyata ,  Sujatha Sankaran ,  Theodorus Eduardus Standaert ,  Ricardo Donaton

发明人： Koji Miyata ,  Sujatha Sankaran ,  Theodorus Eduardus Standaert ,  Ricardo Donaton

IPC分类号： H01L21/44

CPC分类号： H01L21/76811 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76813

摘要： A method and apparatus is provided for fabricating a damascene interconnection. The method begins by forming on a substrate an organosilicate dielectric layer, a capping layer on the organosilicate dielectric layer, and a resist pattern over the capping layer to define a first interconnect opening. The capping layer is etched through the resist pattern using a first etchant. The resist pattern is removed after etching the capping layer. The dielectric layer is etched through the capping layer using a second etchant different from the first etchant to form the first interconnect opening. An interconnection is completed by filling the first interconnect opening with conductive material.

摘要翻译： 提供了一种用于制造镶嵌互连的方法和装置。 该方法开始于在基底上形成有机硅酸盐介电层，有机硅酸盐介电层上的覆盖层，以及覆盖层上的抗蚀剂图案，以限定第一互连开口。 使用第一蚀刻剂将覆盖层蚀刻通过抗蚀剂图案。 在蚀刻覆盖层之后去除抗蚀剂图案。 使用不同于第一蚀刻剂的第二蚀刻剂，通过覆盖层蚀刻电介质层以形成第一互连开口。 通过用导电材料填充第一互连开口来完成互连。

公开(公告)号：US20070057374A1

公开(公告)日：2007-03-15

申请号：US11162513

申请日：2005-09-13

申请人： Paul McLaughlin ,  Sujatha Sankaran ,  Theodorus Standaert

发明人： Paul McLaughlin ,  Sujatha Sankaran ,  Theodorus Standaert

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/31144 ,  H01L21/3212 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/76885

摘要： A semiconductor interconnect structure and method providing an embedded barrier layer to prevent damage to the dielectric material during or after Chemical Mechanical Polishing. The method employs a combination of an embedded film, etchback, using either selective CoWP or a conformal cap such as a SiCNH film, to protect the dielectric material from the CMP process as well as subsequent etch, clean and deposition steps of the next interconnect level.

摘要翻译： 一种半导体互连结构和方法，提供嵌入的阻挡层，以防止在化学机械抛光期间或之后损坏电介质材料。 该方法采用嵌入膜，回蚀，使用选择性CoWP或诸如SiCNH膜的共形盖的组合来保护介电材料免受CMP工艺以及随后的下一个互连级别的蚀刻，清洁和沉积步骤 。

公开(公告)号：US20070032055A1

公开(公告)日：2007-02-08

申请号：US11161538

申请日：2005-08-08

申请人： Theodorus Standaert ,  William Brearley ,  Stephen Greco ,  Sujatha Sankaran

发明人： Theodorus Standaert ,  William Brearley ,  Stephen Greco ,  Sujatha Sankaran

IPC分类号： H01L21/20

CPC分类号： H01L21/76808 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/76847 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for a composite stud contact interface with a decreased contact resistance and improved reliability. A selective dry etch is used which comprises a fluorine containing gas. The contact resistance is reduced by partially dry-etching back the tungsten contact after or during the M1 RIE process. The recessed contact is then subsequently metalized during the M1 liner/plating process. The tungsten contact height is reduced after it has been fully formed.

摘要翻译： 具有降低的接触电阻和改善的可靠性的复合螺柱接触界面的方法和结构。 使用包含含氟气体的选择性干蚀刻。 在M1 RIE工艺过程中或之后，通过部分干法蚀刻钨触点来降低接触电阻。 然后在M1衬套/电镀工艺期间将凹陷接触件金属化。 钨接触高度在完全成型后减小。