公开(公告)号：US09812548B2

公开(公告)日：2017-11-07

申请号：US15247510

申请日：2016-08-25

Applicant: MaxPower Semiconductor, Inc.

Inventor： Richard A. Blanchard ,  Mohamed N. Darwish ,  Jun Zeng

IPC: H01L21/04 ,  H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/10 ,  H01L29/06 ,  H01L29/16 ,  H01L21/265 ,  H01L29/423 ,  H01L29/08 ,  H01L29/417

CPC classification number: H01L29/66068 ,  H01L21/047 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1037 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7813

Abstract: In one embodiment, a power MOSFET vertically conducts current. A bottom electrode may be connected to a positive voltage, and a top electrode may be connected to a low voltage, such as a load connected to ground. A gate and/or a field plate, such as polysilicon, is within a trench. The trench has a tapered oxide layer insulating the polysilicon from the silicon walls. The oxide is much thicker near the bottom of the trench than near the top to increase the breakdown voltage. The tapered oxide is formed by implanting nitrogen into the trench walls to form a tapered nitrogen dopant concentration. This forms a tapered silicon nitride layer after an anneal. The tapered silicon nitride variably inhibits oxide growth in a subsequent oxidation step.

公开(公告)号：US20160359029A1

公开(公告)日：2016-12-08

申请号：US15240831

申请日：2016-08-18

Applicant: MaxPower Semiconductor, Inc.

Inventor： Jun Zeng ,  Mohamed N. Darwish ,  Kui Pu ,  Shih-Tzung Su

IPC: H01L29/739 ,  H01L29/66 ,  H01L29/10 ,  H01L29/423 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L29/7397 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

Abstract: In one embodiment, a power MOSFET cell includes an N+ silicon substrate having a drain electrode. An N-type drift layer is grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed along with a trench having sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well's lateral channel and has a vertical extension into the trench. A positive gate voltage inverts the lateral channel and increases the vertical conduction along the sidewalls to reduce on-resistance. A vertical shield field plate is also located next to the sidewalls and may be connected to the gate. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage. A buried layer and sinker enable the use of a topside drain electrode.

Abstract translation: 在一个实施例中，功率MOSFET单元包括具有漏电极的N +硅衬底。 在衬底上生长N型漂移层。 然后与具有侧壁的沟槽一起形成具有比漂移区更高的掺杂剂浓度的N型层。 在N型层中形成P阱，在P阱中形成N +源极区。 门形成在P阱的横向通道上，并且具有垂直延伸到沟槽中。 正栅极电压反转横向沟道并增加沿着侧壁的垂直传导以降低导通电阻。 垂直屏蔽场板也位于侧壁旁边，并且可以连接到门。 当设备关闭时，场板横向耗尽N型层以增加击穿电压。 掩埋层和沉降片使得能够使用顶侧漏电极。

公开(公告)号：US09419084B2

公开(公告)日：2016-08-16

申请号：US14840744

申请日：2015-08-31

Applicant: MaxPower Semiconductor Inc.

Inventor： Mohamed N. Darwish ,  Jun Zeng

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/10 ,  H01L29/78 ,  H01L29/16 ,  H03K17/687 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/7811 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0856 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/404 ,  H01L29/407 ,  H01L29/408 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/7813 ,  H01L29/7823 ,  H01L29/7827 ,  H01L29/7835 ,  H03K17/687

Abstract: N-channel power semiconductor devices in which an insulated field plate is coupled to the drift region, and immobile electrostatic charge is also present at the interface between the drift region and the insulation around the field plate. The electrostatic charge permits OFF-state voltage drop to occur near the source region, in addition to the voltage drop which occurs near the drain region (due to the presence of the field plate).

公开(公告)号：US09224855B2

公开(公告)日：2015-12-29

申请号：US14168286

申请日：2014-01-30

Applicant: MaxPower Semiconductor, Inc.

Inventor： Jun Zeng ,  Mohamed N. Darwish

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/10 ,  H01L29/40 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7813 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734

Abstract: Power devices, and related process, where both gate and field plate trenches have multiple stepped widths, using self-aligned process steps.

Abstract translation: 功率器件和相关工艺，其中栅极和场板沟槽都具有多个阶梯宽度，采用自对准工艺步骤。

公开(公告)号：US09184248B2

公开(公告)日：2015-11-10

申请号：US14616395

申请日：2015-02-06

Applicant: MaxPower Semiconductor, Inc.

Inventor： Jun Zeng ,  Mohamed N. Darwish ,  Kui Pu ,  Shih-Tzung Su

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/732 ,  H01L29/40 ,  H01L29/06 ,  H01L29/10 ,  H01L29/739

CPC classification number: H01L29/407 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813

Abstract: A power MOSFET cell includes an N+ silicon substrate having a drain electrode. A low dopant concentration N-type drift layer is grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed and etched to have sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well's lateral channel and has a vertical extension next to the top portion of the sidewalls. A positive gate voltage inverts the lateral channel and increases the conduction along the sidewalls to reduce on-resistance. A vertical shield field plate is also located next to the sidewalls and extends virtually the entire length of the sidewalls. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage.

Abstract translation: 功率MOSFET单元包括具有漏电极的N +硅衬底。 在衬底上生长低掺杂浓度的N型漂移层。 然后形成具有比漂移区更高的掺杂剂浓度的N型层并蚀刻以具有侧壁。 在N型层中形成P阱，在P阱中形成N +源极区。 栅极形成在P阱的横向通道上，并且具有靠近侧壁顶部的垂直延伸。 正栅极电压反转横向沟道并增加沿侧壁的导通以降低导通电阻。 垂直屏蔽场板也位于侧壁旁边，几乎延伸到侧壁的整个长度上。 当设备关闭时，场板横向耗尽N型层以增加击穿电压。

公开(公告)号：US09129936B2

公开(公告)日：2015-09-08

申请号：US13975421

申请日：2013-08-26

Applicant: MaxPower Semiconductor, Inc.

Inventor： Mohamed N. Darwish ,  Jun Zeng

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/7811 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0856 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/404 ,  H01L29/407 ,  H01L29/408 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/7813 ,  H01L29/7823 ,  H01L29/7827 ,  H01L29/7835 ,  H03K17/687

Abstract: N-channel power semiconductor devices in which an insulated field plate is coupled to the drift region, and immobile electrostatic charge is also present at the interface between the drift region and the insulation around the field plate. The electrostatic charge permits OFF-state voltage drop to occur near the source region, in addition to the voltage drop which occurs near the drain region (due to the presence of the field plate).

Abstract translation: 其中绝缘场板耦合到漂移区的N沟道功率半导体器件，并且固定静电电荷也存在于漂移区和场板周围的绝缘体之间的界面处。 除了在漏极区附近发生的电压降（由于场板的存在）外，静电电荷还允许在源极区域附近发生OFF状态电压降。

公开(公告)号：US20150221765A1

公开(公告)日：2015-08-06

申请号：US14338303

申请日：2014-07-22

Applicant: MaxPower Semiconductor, Inc.

Inventor： Jun Zeng ,  Mohamed N. Darwish ,  Kui Pu ,  Shih-Tzung Su

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/10 ,  H01L29/739 ,  H01L29/40

CPC classification number: H01L29/7813 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0834 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811

Abstract: A power MOSFET cell includes an N+ silicon substrate having a drain electrode. A low dopant concentration N-type drift layer is grown over the substrate. Alternating N and P-type columns are formed over the drift layer with a higher dopant concentration. An N-type layer, having a higher dopant concentration than the drift region, is then formed and etched to have sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well's lateral channel and next to the sidewalls as a vertical field plate. A source electrode contacts the P-well and source region. A positive gate voltage inverts the lateral channel and increases the conduction along the sidewalls. Current between the source and drain flows laterally and then vertically through the various N layers. On resistance is reduced and the breakdown voltage is increased.

Abstract translation: 功率MOSFET单元包括具有漏电极的N +硅衬底。 在衬底上生长低掺杂浓度的N型漂移层。 在漂移层上形成交替的N型和P型列，掺杂浓度较高。 然后形成具有比漂移区更高的掺杂剂浓度的N型层并蚀刻以具有侧壁。 在N型层中形成P阱，在P阱中形成N +源极区。 在P阱的横向通道上形成一个栅极，并且在侧壁上形成一个垂直场板。 源电极接触P阱和源极区。 正栅极电压反转横向沟道并增加沿着侧壁的导电。 源极和漏极之间的电流横向流动，然后垂直穿过各种N层。 导通电阻降低，击穿电压增加。

公开(公告)号：US08847307B2

公开(公告)日：2014-09-30

申请号：US13693714

申请日：2012-12-04

Applicant: MaxPower Semiconductor, Inc.

Inventor： Mohamed N. Darwish ,  Jun Zeng ,  Richard A. Blanchard

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/40 ,  H01L29/861 ,  H01L29/10 ,  H01L21/265 ,  H01L29/08

CPC classification number: H01L29/0611 ,  H01L21/26586 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0661 ,  H01L29/0873 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8611

Abstract: Power devices using refilled trenches with permanent charge at or near their sidewalls. These trenches extend vertically into a drift region.

Abstract translation: 使用重新焊接的沟槽的功率器件在其侧壁处或附近具有永久电荷。 这些沟槽垂直延伸到漂移区域。

公开(公告)号：US20140239386A1

公开(公告)日：2014-08-28

申请号：US14168286

申请日：2014-01-30

Applicant: MaxPower Semiconductor, Inc.

Inventor： Jun Zeng ,  Mohamed N. Darwish

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734

Abstract: Power devices, and related process, where both gate and field plate trenches have multiple stepped widths, using self-aligned process steps.

Abstract translation: 功率器件和相关工艺，其中栅极和场板沟槽都具有多个阶梯宽度，采用自对准工艺步骤。

公开(公告)号：US20140042525A1

公开(公告)日：2014-02-13

申请号：US13758703

申请日：2013-02-04

Applicant: MaxPower Semiconductor, Inc.

Inventor： Mohamed N. Darwish ,  Jun Zeng ,  Richard A. Blanchard

IPC: H01L27/088

CPC classification number: H01L29/66734 ,  H01L21/26506 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/36 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/7395 ,  H01L29/7803 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7831 ,  H01L29/7835

Abstract: Methods and systems for power semiconductor devices integrating multiple quasi-vertical transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.

Abstract translation: 用于在单个芯片上集成多个准垂直晶体管的功率半导体器件的方法和系统。 多个功率晶体管（或有源区）并联，但一个晶体管具有较低的阈值电压。 当晶体管正向偏置时，这降低了电压降。 在替代实施例中，具有较低阈值电压的功率器件简单地连接为耗尽二极管，从而分流有源晶体管的体二极管，而不会影响导通和导通状态。