公开(公告)号：US11586386B2

公开(公告)日：2023-02-21

申请号：US17315532

申请日：2021-05-10

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave ,  Thomas H. Kinsley ,  Matthew A. Prather

IPC: G06F3/06 ,  G11C7/10 ,  G11C11/4093 ,  G06F13/40

Abstract: Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication. The device may transmit, from the first portion, a signal instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The signal may be provided at an ODT I/O terminal of the first portion coupled to an ODT I/O terminal of the second portion.

公开(公告)号：US20210312958A1

公开(公告)日：2021-10-07

申请号：US16839893

申请日：2020-04-03

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave

IPC: G11C7/10 ,  H03K19/00 ,  H03K19/0175 ,  G11C29/02 ,  G11C29/50

Abstract: Memory devices and systems with per pin input/output termination and driver impedance calibration capabilities, and associated methods, are disclosed herein. In one embodiment, a device apparatus includes circuitry dedicated to an individual DQ pin of the device apparatus. The circuitry can be configured to (i) generate, at least in part, a voltage at the DQ pin based, at least in part, on an impedance internal to a host device electrically connected to the device apparatus and (ii) compare the voltage to a target voltage. Based, at least in part, on the comparison, the circuitry can be configured to adjust a resistance of an output driver and/or a termination circuit of the device apparatus that correspond to the DQ pin to adjust the impedance of the output driver and/or termination circuit to match an impedance associated with a corresponding input/output pin of the host device.

公开(公告)号：US20210072287A1

公开(公告)日：2021-03-11

申请号：US16985156

申请日：2020-08-04

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Stewart ,  Eric J. Stave ,  Matthew A. Prather

IPC: G01R13/32 ,  H04L1/24 ,  H04L1/20

Abstract: A method of operating an oscilloscope is disclosed. The method comprises providing a bit stream comprising pseudo-random data to an oscilloscope across a data path characterized by sufficient signal degradation to prevent the oscilloscope from reliably triggering a sweep of an eye pattern based on receiving the pseudo-random data; inserting a predetermined sequence of bits into the bit stream at predetermined periodic intervals to open the eye pattern sufficiently during each of the periodic intervals to permit the oscilloscope to trigger the sweep of the eye pattern; and generating the eye pattern based at least in part on the pseudo-random data and excluding the predetermined sequence of bits from the sweep of the eye pattern. Oscilloscopes configured to trigger according to a predetermined system of bits at predetermined intervals are also disclosed.

公开(公告)号：US20210035617A1

公开(公告)日：2021-02-04

申请号：US16530739

申请日：2019-08-02

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave ,  George E. Pax ,  Yogesh Sharma ,  Gregory A. King ,  Chan H. Yoo ,  Randon K. Richards ,  Timothy M. Hollis

IPC: G11C7/22 ,  G11C7/10 ,  G11C16/10

Abstract: Systems, apparatuses, and methods for operating a memory device or devices are described. A memory device or module may introduce latency in commands to coordinate operations at the device or to improve timing or power consumption at the device. For example, a host may issue a command to a memory module, and a component or feature of the memory module may receive the command and modify the command or the timing of its execution in manner that is invisible or non-disruptive to the host while facilitating operations at the memory module. In some examples, components or features of a memory module may be disabled to effect or introduce latency in operation without affecting timing or operation of a host device. A memory module may operate in different modes that allow for different latencies; the use or introduction of latencies may not affect other features or operability of the memory module.

公开(公告)号：US20250165340A1

公开(公告)日：2025-05-22

申请号：US18901895

申请日：2024-09-30

Applicant: Micron Technology, Inc.

Inventor： Jennifer E. Taylor ,  Timothy M. Hollis ,  Eric J. Stave ,  Chulkyu Lee ,  Chris Gregory Holub

IPC: G06F11/10

Abstract: A decision counter circuit is used in a self-adaptation circuit to apply digital averaging to input signals to obtain adaptive settings of circuit parameters for a memory chip of a memory device during the operation. Individual adaptive settings of the parameters (e.g., impedance, capacitance, equalization parameters) during operation are obtained for each of the memory chips in the memory device. The self-adaptation enables equalization adjustment across temperature and voltage drift.

公开(公告)号：US20240420789A1

公开(公告)日：2024-12-19

申请号：US18638379

申请日：2024-04-17

Applicant: Micron Technology, Inc.

Inventor： Jennifer E. Taylor ,  Eric J. Stave ,  Timothy M. Hollis ,  Chulkyu Lee ,  Chris Gregory Holub

IPC: G11C29/12 ,  G11C29/20

Abstract: Systems and methods include self-training an equalizer of a semiconductor device using the semiconductor device. The semiconductor device receives an indication of a condition for re-training of the equalizer. The semiconductor device operates the equalizer based on trained values derived during the self-training. The semiconductor device also determines that the condition has been met, and in response, the semiconductor device re-trains the equalizer without invocation of re-training by a host device coupled to the semiconductor device.

公开(公告)号：US12068751B2

公开(公告)日：2024-08-20

申请号：US17852657

申请日：2022-06-29

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave ,  Tyler J. Gomm

IPC: G11C11/4076 ,  G11C7/22 ,  H03K5/1534 ,  H03K5/156 ,  H03K19/21

CPC classification number: H03K5/1565 ,  G11C7/222 ,  H03K5/1534 ,  H03K19/21

Abstract: A device includes a clock input circuit that when in operation receives a clock signal and transmits an internal clock signal based on the clock signal. The device also includes an internal clock generator coupled to the clock input circuit to receive the internal clock signal, wherein the internal clock generator comprises clock adjustment circuitry that when in operation generates a phase controlled internal clock signal having subsequent clock edges based upon a single clock edge of the internal clock signal, wherein the phase controlled internal clock signal comprises a first frequency as a multiple of a second frequency of the internal clock signal.

公开(公告)号：US11948661B2

公开(公告)日：2024-04-02

申请号：US17244942

申请日：2021-04-29

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave ,  Dirgha Khatri ,  Elancheren Durai ,  Quincy R. Holton ,  Timothy M. Hollis ,  Matthew B. Leslie ,  Baekkyu Choi ,  Boe L Holbrook ,  Yogesh Sharma ,  Scott R. Cyr

IPC: G11C8/18 ,  G11C7/10 ,  G11C8/06 ,  G11C8/12

CPC classification number: G11C8/18 ,  G11C7/1096 ,  G11C8/06 ,  G11C8/12

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which clock trees can be separately optimized to provide a coarse alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal), and/or in which individual memory devices can be isolated for fine-tuning of device-specific alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal). Moreover, individual memory devices can be isolated for fine-tuning of device-specific equalization of a command/address signal (and/or a chip select signal or other control signal).

公开(公告)号：US11494323B2

公开(公告)日：2022-11-08

申请号：US17387319

申请日：2021-07-28

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave

IPC: G06F13/16 ,  G06F13/40 ,  G11C11/4076 ,  G11C11/4074 ,  G11C11/4072

Abstract: Methods, systems, and devices for addressing scheme for a memory system are described. A memory system may include a plurality of memory devices that are coupled with various command address (CA) channels via respective pins. In some examples, different pins of each memory device may be coupled with different CA channels. When the memory system receives a command to enter a memory device into a per-device addressability (PDA) mode, certain CA channels may be driven. One or more memory devices may enter the PDA mode based on certain pins of the respective memory device being biased.

公开(公告)号：US11416437B2

公开(公告)日：2022-08-16

申请号：US16720976

申请日：2019-12-19

Applicant: Micron Technology, Inc.

Inventor： Thomas H. Kinsley ,  George E. Pax ,  Timothy M. Hollis ,  Yogesh Sharma ,  Randon K. Richards ,  Chan H. Yoo ,  Gregory A. King ,  Eric J. Stave

IPC: G06F13/42 ,  G11C7/10 ,  G06F11/10

Abstract: An apparatus is provided, comprising a plurality of memory devices and a buffering device that permits memory devices with a variety of physical dimensions and memory formats to be used in an industry-standard memory module format. The buffering device includes memory interface circuitry and at least one first-in first-out (FIFO) or multiplexer circuit. The apparatus further comprises a parallel bus connecting the buffering device to the plurality of memory devices. The parallel bus includes a plurality of independent control lines, each coupling the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices. The parallel bus further includes a plurality of independent data channels, each coupling the at least one FIFO circuit or multiplexer circuit to a corresponding subset of a plurality of second subsets of the plurality of memory devices.