公开(公告)号：US20240028253A1

公开(公告)日：2024-01-25

申请号：US18224538

申请日：2023-07-20

Applicant: Micron Technology, Inc.

Inventor： Avinash Rajagiri ,  Ching-Huang Lu ,  Aman Gupta ,  Shuji Tanaka ,  Masashi Yoshida ,  Shinji Sato ,  Yingda Dong

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory device can include a memory array coupled with a control logic. The control logic initiates a program operation on the memory array, the program operation including a program phase and a program recovery phase. The control logic causes a program voltage to be applied to a selected word line during the program phase. The control logic causes a select gate drain coupled with a string of memory cells to deactivate during the program recovery phase after applying the program voltage, where the string of memory cells include a plurality of memory cells each coupled to a corresponding word line of a plurality of wordlines. The control logic causes a voltage to be applied to a select gate source coupled with the string of memory cells to activate the select gate source during the program recovery phase concurrent to causing the select gate drain to deactivate.

公开(公告)号：US20220351785A1

公开(公告)日：2022-11-03

申请号：US17861502

申请日：2022-07-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Shuji Tanaka ,  Masashi Yoshida ,  Masanobu Saito ,  Yoshihiko Kamata

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/10

Abstract: Memory might include a plurality of series-connected non-volatile memory cells, a plurality of series-connected first field-effect transistors connected in series with the plurality of series-connected non-volatile memory cells, and a second field-effect transistor, wherein the channel of the second field-effect transistor is capacitively coupled to channels of the plurality of series-connected first field-effect transistors. The memory might further include a controller configured to cause the memory to selectively activate a selected non-volatile memory cell, activate each remaining non-volatile memory cell, increase a voltage level of the respective channel of each first field-effect transistor, selectively discharge the voltage level of the respective channel of each first field-effect transistor through the selected non-volatile memory cell, and determine whether the second field-effect transistor is activated in response to a remaining voltage level of the respective channel of each first field-effect transistor.

公开(公告)号：US20240412790A1

公开(公告)日：2024-12-12

申请号：US18806931

申请日：2024-08-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Shuji Tanaka ,  Masashi Yoshida ,  Masanobu Saito ,  Yoshihiko Kamata

IPC: G11C16/26 ,  G11C16/04

Abstract: Apparatus might include a plurality of series-connected first field-effect transistors selectively connected in series with a plurality of series-connected second field-effect transistors, wherein the plurality of series-connected first field-effect transistors are configured to store user data, and wherein a channel of the plurality of series-connected second transistors is capacitively coupled to a channel of a third transistor.

公开(公告)号：US12112805B2

公开(公告)日：2024-10-08

申请号：US17889471

申请日：2022-08-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Shuji Tanaka ,  Masanobu Saito

IPC: G11C16/10 ,  G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/10 ,  G11C16/0483 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: Apparatus might include an array of memory cells comprising a plurality of strings of series-connected memory cells, a data line, a plurality of sets of field-effect transistors with each of the sets of field-effect transistors between the data line and a respective string of series-connected memory cells and having N field-effect transistors that are fabricated to have a respective binary permutation of two threshold voltages of a plurality of possible binary permutations of two threshold voltages having N positions, and N select lines that are each connected to a control gate of a respective field-effect transistor of each of the sets of field-effect transistors.

公开(公告)号：US20240021219A1

公开(公告)日：2024-01-18

申请号：US17812118

申请日：2022-07-12

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi ,  Shuji Tanaka ,  Yoshihiko Kamata ,  Jun Fujiki ,  Tomoharu Tanaka

IPC: G11C5/06 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C5/063 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L23/5226 ,  H01L23/5283 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: A microelectronic device comprises a stack structure, pillar structures, a conductive plug structure, a sense transistor, and selector transistors. The stack structure comprises a vertically alternating sequence of conductive material and insulative material, and is divided into blocks separated by dielectric slot structures. The blocks individually include sub-blocks horizontally extending in parallel with one another. The pillar structures vertically extend through one of the blocks of the stack structure. Each pillar structure of a group of the pillar structures is positioned within a different one of the sub-blocks of the one of the blocks than each other pillar structure of the group. The conductive plug structure is coupled to multiple of the pillar structures of the group of the pillar structures. The sense transistor is gated by the conductive plug structure. The selector transistors couple the sense transistor to a read source line structure and a digit line structure.

公开(公告)号：US11670379B2

公开(公告)日：2023-06-06

申请号：US17111751

申请日：2020-12-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Shuji Tanaka ,  Masashi Yoshida ,  Masanobu Saito ,  Yoshihiko Kamata

IPC: G11C7/00 ,  G11C16/26 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  G11C16/04 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  G11C16/24 ,  G11C16/08 ,  H01L27/11565

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582

Abstract: Arrays of memory cells might include a data line, a source, a plurality of pass gates connected in series between the data line and the source, a plurality of unit column structures each having a respective plurality of series-connected non-volatile memory cells connected in series with a respective plurality of series-connected field-effect transistors, wherein a channel of each non-volatile memory cell of its respective plurality of series-connected non-volatile memory cells and a channel of each field-effect transistor of its respective plurality of series-connected field-effect transistors are selectively connected to one another, and a plurality of backside gate lines each connected to the second control gate of a respective pass gate of the plurality of pass gates, wherein, for each unit column structure of the plurality of unit column structures, the channel of a particular field-effect transistor of its respective plurality of field-effect transistors is capacitively coupled to the first channel of a respective pass gate of the plurality of pass gates.

公开(公告)号：US11657880B2

公开(公告)日：2023-05-23

申请号：US17861502

申请日：2022-07-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Shuji Tanaka ,  Masashi Yoshida ,  Masanobu Saito ,  Yoshihiko Kamata

IPC: G11C7/00 ,  G11C16/26 ,  G11C16/04 ,  G11C16/10 ,  G11C11/56 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11556

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/10 ,  G11C11/5628 ,  G11C11/5671 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

Abstract: Memory might include a plurality of series-connected non-volatile memory cells, a plurality of series-connected first field-effect transistors connected in series with the plurality of series-connected non-volatile memory cells, and a second field-effect transistor, wherein the channel of the second field-effect transistor is capacitively coupled to channels of the plurality of series-connected first field-effect transistors. The memory might further include a controller configured to cause the memory to selectively activate a selected non-volatile memory cell, activate each remaining non-volatile memory cell, increase a voltage level of the respective channel of each first field-effect transistor, selectively discharge the voltage level of the respective channel of each first field-effect transistor through the selected non-volatile memory cell, and determine whether the second field-effect transistor is activated in response to a remaining voltage level of the respective channel of each first field-effect transistor.

公开(公告)号：US20230085034A1

公开(公告)日：2023-03-16

申请号：US17889471

申请日：2022-08-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Shuji Tanaka ,  Masanobu Saito

IPC: G11C16/10 ,  G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: Apparatus might include an array of memory cells comprising a plurality of strings of series-connected memory cells, a data line, a first field-effect transistor between the data line and a first string of series-connected memory cells, and a second field-effect transistor between the data line and a second string of series-connected memory cells, wherein a control gate of the first field-effect transistor is connected to a control gate of the second field-effect transistor, and wherein a channel of the first field-effect transistor was fabricated to have a first threshold voltage and a channel of the second field-effect transistor was fabricated to have a second threshold voltage, different than the first threshold voltage.

公开(公告)号：US20220181346A1

公开(公告)日：2022-06-09

申请号：US17557389

申请日：2021-12-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Shuji Tanaka ,  Masashi Yoshida ,  Masanobu Saito ,  Yoshihiko Kamata

IPC: H01L27/11556 ,  G11C16/34 ,  G11C5/06 ,  G11C5/02 ,  H01L27/11582

Abstract: Arrays of memory cells might include a first upper data line, a second upper data line, a lower data line, a first pass gate selectively connected to the lower data line, a second pass gate connected to the first pass gate and selectively connected to the lower data line, a third pass gate selectively connected to the lower data line, a fourth pass gate connected to the third pass gate and selectively connected to the lower data line, unit column structures selectively connected to a respective one of the upper data lines and capacitively coupled to a first channel of a respective one of the pass gates, and control lines capacitively coupled to a second channel of a respective one of the pass gates.

公开(公告)号：US20220180938A1

公开(公告)日：2022-06-09

申请号：US17111751

申请日：2020-12-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Shuji Tanaka ,  Masashi Yoshida ,  Masanobu Saito ,  Yoshihiko Kamata

IPC: G11C16/26 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  G11C16/24 ,  G11C16/08 ,  G11C16/04

Abstract: Arrays of memory cells might include a data line, a source, a plurality of pass gates connected in series between the data line and the source, a plurality of unit column structures each having a respective plurality of series-connected non-volatile memory cells connected in series with a respective plurality of series-connected field-effect transistors, wherein a channel of each non-volatile memory cell of its respective plurality of series-connected non-volatile memory cells and a channel of each field-effect transistor of its respective plurality of series-connected field-effect transistors are selectively connected to one another, and a plurality of backside gate lines each connected to the second control gate of a respective pass gate of the plurality of pass gates, wherein, for each unit column structure of the plurality of unit column structures, the channel of a particular field-effect transistor of its respective plurality of field-effect transistors is capacitively coupled to the first channel of a respective pass gate of the plurality of pass gates.