公开(公告)号：US20240071918A1

公开(公告)日：2024-02-29

申请号：US17822421

申请日：2022-08-25

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Sidhartha Gupta ,  Indra V. Chary ,  Richard J. Hill ,  Umberto Maria Meotto

IPC: H01L23/528 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/5283 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582

Abstract: A microelectronic device includes a stack structure having tiers each including conductive material vertically neighboring insulative material and conductive contact structures. The stack structure is divided into blocks horizontally extending in parallel in a first direction and separated from one another in a second direction orthogonal to the first direction by insulative slot structures. At least one of the blocks includes a lower stadium structure having steps including edges of some of the tiers, and an upper stadium structure vertically overlying the lower stadium structure and having additional steps including edges of some other of the tiers vertically overlying the some of the tiers. The additional steps have greater tread widths in the first direction than the steps. Conductive contact structures are in contact with the additional steps of the upper stadium structure of the at least one of the blocks. Memory devices and electronic systems are also described.

公开(公告)号：US20230276624A1

公开(公告)日：2023-08-31

申请号：US17682514

申请日：2022-02-28

Applicant: Micron Technology, Inc.

Inventor： Pankaj Sharma ,  Naveen Kaushik ,  Sidhartha Gupta

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11573 ,  G11C16/04 ,  H01L29/423 ,  H01L21/28 ,  H01L29/41 ,  H01L29/51

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11573 ,  G11C16/0483 ,  H01L29/42344 ,  H01L29/40117 ,  H01L29/413 ,  H01L29/517

Abstract: An electronic device comprises a stack comprising tiers of alternating conductive structures and insulative structures, and pillars vertically extending through the stack. The pillars comprise a tunnel dielectric material, a channel material, and an insulative material substantially surrounded by the channel material. The electronic device comprises a memory material horizontally adjacent to the conductive structures without being horizontally adjacent to the insulative structures. Related memory devices, systems, and methods of forming the electronic devices are also described.

公开(公告)号：US20220384242A1

公开(公告)日：2022-12-01

申请号：US17818317

申请日：2022-08-08

Applicant: Micron Technology, Inc.

Inventor： Sidhartha Gupta ,  David Ross Economy ,  Richard J. Hill ,  Kyle A. Ritter ,  Naveen Kaushik

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/11582 ,  H01L27/11556

Abstract: A method of forming an apparatus includes forming pillar structures extending vertically through a first isolation material, forming conductive lines operatively coupled to the pillar structures, forming dielectric structures overlying the conductive lines, and forming air gaps between neighboring conductive lines. The air gaps are laterally adjacent to the conductive lines with a portion of the air gaps extending above a plane of an upper surface of the laterally adjacent conductive lines and a portion of the air gaps extending below a plane of a lower surface of the laterally adjacent conductive lines. Apparatuses, memory devices, methods of forming a memory device, and electronic systems are also disclosed.

公开(公告)号：US20220199641A1

公开(公告)日：2022-06-23

申请号：US17127971

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Matthew J. King ,  Sidhartha Gupta ,  Paolo Tessariol ,  Kunal Shrotri ,  Kye Hyun Baek ,  Kyle A. Ritter ,  Shuji Tanaka ,  Umberto Maria Meotto ,  Richard J. Hill ,  Matthew Holland

IPC: H01L27/11582 ,  H01L27/11556

Abstract: A microelectronic device comprises a stack structure comprising a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, strings of memory cells vertically extending through the block structures of the stack structure, the strings of memory cells individually comprising a channel material vertically extending through the stack structure, an additional stack structure vertically overlying the stack structure and comprising a vertical sequence of additional conductive structures and additional insulative structures arranged in additional tiers, first pillars extending through the additional stack structure and vertically overlying the strings of memory cells, each of the first pillars horizontally offset from a center of a corresponding string of memory cells, second pillars extending through the additional stack structure and vertically overlying the strings of memory cells, and additional slot structures comprising a dielectric material extending through at least a portion of the additional stack structure and sub-dividing each of the block structures into sub-block structures, the additional slot structures horizontally neighboring the first pillars. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US12137553B2

公开(公告)日：2024-11-05

申请号：US17395211

申请日：2021-08-05

Applicant: Micron Technology, Inc.

Inventor： Sidhartha Gupta ,  Naveen Kaushik ,  Pankaj Sharma

IPC: H10B41/27 ,  H01L23/538 ,  H10B43/27

Abstract: A method used in forming a memory array comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory-cell strings extend through the insulative and conductive tiers. Conductive vias are formed above and individually electrically coupled to individual of the channel-material strings. Insulating material is laterally-between immediately-adjacent of the conductive vias. At least some of the insulating material is vertically removed to form an upwardly-open void-space that is circumferentially about multiple of the conductive vias. Insulative material is formed laterally-between the immediately-adjacent conductive vias to form a covered void-space from the upwardly-open void-space. Digitlines are formed above that are individually electrically coupled to a plurality of individual of the conductive vias there-below. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US12119176B2

公开(公告)日：2024-10-15

申请号：US17179890

申请日：2021-02-19

Applicant: Micron Technology, Inc.

Inventor： Pankaj Sharma ,  Sidhartha Gupta

IPC: H01G11/26 ,  H01G11/08 ,  H01G11/36 ,  H01G11/86 ,  H01L25/00 ,  H01L25/16 ,  H01L49/02 ,  H10B99/00 ,  H01G11/52 ,  H01G11/58

CPC classification number: H01G11/26 ,  H01G11/08 ,  H01G11/36 ,  H01G11/86 ,  H01L25/16 ,  H01L25/50 ,  H01L28/75 ,  H01L28/86 ,  H01L28/88 ,  H10B99/00 ,  H01G11/52 ,  H01G11/58

Abstract: Some embodiments include an integrated assembly having a supercapacitor supported by a semiconductor substrate. The supercapacitor includes first and second electrode bases. The first electrode base includes first laterally-projecting regions, and the second electrode base includes second laterally-projecting regions which are interdigitated with the first laterally-projecting regions. A distance between the first and second laterally-projecting regions is less than or equal to about 500 nm. Carbon nanotubes extend upwardly from the first and second electrode bases. The carbon nanotubes are configured as a first membrane structure associated with the first electrode base and as a second membrane structure associated with the second electrode base. Pseudocapacitive material is dispersed throughout the first and second membrane structures. Electrolyte material is within and between the first and second membrane structures. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20240206175A1

公开(公告)日：2024-06-20

申请号：US18540147

申请日：2023-12-14

Applicant: Micron Technology, Inc.

Inventor： Sidhartha Gupta ,  Adam W. Saxler ,  Andrew Li ,  John D. Hopkins

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers directly above a conductor tier. The first tiers comprise sacrificial material and the second tiers comprise non-sacrificial material that is of different composition from that of the sacrificial material. The stack comprises horizontally-elongated trenches extending through the first tiers and the second tiers and are individually between immediately-laterally-adjacent memory-block regions. Channel-material strings are formed that extend through the first and second tiers in the memory-block regions. Through the horizontally-elongated trenches, the sacrificial material is replaced with conductive material that comprises control-gate lines in the memory-block regions. After the replacing, conducting material is formed in a lowest of the first tiers and directly electrically couples together the channel material of the channel-material strings and conductor material of the conductor tier. Other embodiments, including structure, are disclosed.

公开(公告)号：US20240081076A1

公开(公告)日：2024-03-07

申请号：US17929911

申请日：2022-09-06

Applicant: Micron Technology, Inc.

Inventor： Sidhartha Gupta ,  Matthew J. King ,  Jiewei Chen ,  Yi Hu

IPC: H01L27/11575 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L27/11575 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11582

Abstract: An electronic device comprises a stack comprising tiers of alternating conductive structures and insulative structures adjacent to a source, and strings of memory cells extending vertically through the stack. The strings of memory cells individually comprising a channel material extending vertically through the stack. The electronic device comprises an additional stack adjacent to the stack and comprising tiers of alternating additional conductive structures and additional insulative structures, pillars extending through the additional stack and adjacent to the strings of memory cells, conductive contacts adjacent to the pillars, and isolation structures laterally intervening between neighboring pillars. The isolation structures exhibit a weave pattern, and portions of the isolation structures are laterally adjacent to and physically contact the conductive contacts. Related memory devices, systems, and methods are also described.

公开(公告)号：US20220415917A1

公开(公告)日：2022-12-29

申请号：US17822708

申请日：2022-08-26

Applicant: Micron Technology, Inc.

Inventor： Daniel Billingsley ,  Matthew J. King ,  Jordan D. Greenlee ,  Yongjun J. Hu ,  Tom George ,  Amritesh Rai ,  Sidhartha Gupta ,  Kyle A. Ritter

IPC: H01L27/11573 ,  H01L27/11582 ,  H01L27/11556 ,  H01L21/28 ,  H01L29/49 ,  H01L27/11529

Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, each of the tiers individually comprising a conductive structure and an insulative structure, strings of memory cells vertically extending through the stack structure, the strings of memory cells comprising a channel material vertically extending through the stack structure, and another stack structure vertically overlying the stack structure and comprising other tiers of alternating levels of other conductive structures and other insulative structures, the other conductive structures exhibiting a conductivity greater than a conductivity of the conductive structures of the stack structure. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US11456208B2

公开(公告)日：2022-09-27

申请号：US16990463

申请日：2020-08-11

Applicant: Micron Technology, Inc.

Inventor： Sidhartha Gupta ,  David Ross Economy ,  Richard J. Hill ,  Kyle A. Ritter ,  Naveen Kaushik

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/11582 ,  H01L27/11556

Abstract: A method of forming an apparatus includes forming pillar structures extending vertically through a first isolation material, forming conductive lines operatively coupled to the pillar structures, forming dielectric structures overlying the conductive lines, and forming air gaps between neighboring conductive lines. The air gaps are laterally adjacent to the conductive lines with a portion of the air gaps extending above a plane of an upper surface of the laterally adjacent conductive lines and a portion of the air gaps extending below a plane of a lower surface of the laterally adjacent conductive lines. Apparatuses, memory devices, methods of forming a memory device, and electronic systems are also disclosed.