公开(公告)号：US20230039517A1

公开(公告)日：2023-02-09

申请号：US17396056

申请日：2021-08-06

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  John D. Hopkins ,  Purnima Narayanan ,  Vinayak Shamanna ,  Justin D. Shepherdson

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack that will comprise vertically-alternating conductive tiers and insulative tiers. The stack comprises laterally-spaced memory-block regions. The lower portion comprises multiple lower of the conductive tiers and multiple lower of the insulative tiers. The lower insulative tiers comprise insulative material. The lower conductive tiers comprise sacrificial material that is of different composition from that of the insulative material. The sacrificial material is replaced with conducting material. After the replacing of the sacrificial material, the vertically-alternating conductive tiers and insulative tiers of an upper portion of the stack are formed above the lower portion. The upper portion comprises multiple upper of the conductive tiers and multiple upper of the insulative tiers. The upper insulative tiers comprise insulating material. The upper conductive tiers comprise sacrifice material that is of different composition from that of the conducting material, the insulating material, and the insulative material. The sacrifice material is replaced with conductive material. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20210399006A1

公开(公告)日：2021-12-23

申请号：US16904317

申请日：2020-06-17

Applicant: Micron Technology, Inc.

Inventor： Yifen Liu ,  Tecla Ghilardi ,  George Matamis ,  Justin D. Shepherdson ,  Nancy M. Lomeli ,  Chet E. Carter ,  Erik R. Byers

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: A microelectronic device comprises a first set of tiers, each tier of the first set of tiers comprising alternating levels of a conductive material and an insulative material and having a first tier pitch, a second set of tiers adjacent to the first set of tiers, each tier of the second set of tiers comprising alternating levels of the conductive material and the insulative material and having a second tier pitch less than the first tier pitch, a third set of tiers adjacent to the second set of tiers, each tier of the third set of tiers comprising alternating levels of the conductive material and the insulative material and having a third tier pitch less than the second tier pitch, and a string of memory cells extending through the first set of tiers, the second set of tiers, and the third set of tiers. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US20250063734A1

公开(公告)日：2025-02-20

申请号：US18936523

申请日：2024-11-04

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Justin D. Shepherdson ,  Chet E. Carter

IPC: H10B43/27 ,  H10B43/50

Abstract: A microelectronic device may include a source structure and a stack structure. The stack structure may include a vertically alternating sequence of insulative structures and conductive structures. Filled slits may extend through the stack structure and into the source structure, the slits dividing the stack structure into multiple blocks. Memory cell pillars may extend through the stack structure and into the source structure, the memory cell pillars and the filled slits terminated at substantially the same depth within the source structure as one another.

公开(公告)号：US12137564B2

公开(公告)日：2024-11-05

申请号：US18359792

申请日：2023-07-26

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Justin D. Shepherdson ,  Chet E. Carter

IPC: H10B43/27 ,  H10B43/50

Abstract: A microelectronic device may include a source structure and a stack structure. The stack structure may include a vertically alternating sequence of insulative structures and conductive structures. Filled slits may extend through the stack structure and into the source structure, the slits dividing the stack structure into multiple blocks. Memory cell pillars may extend through the stack structure and into the source structure, the memory cell pillars and the filled slits terminated at substantially the same depth within the source structure as one another.

公开(公告)号：US20240074177A1

公开(公告)日：2024-02-29

申请号：US17822101

申请日：2022-08-24

Applicant: Micron Technology, Inc.

Inventor： David H. Wells ,  Justin D. Shepherdson ,  Swapnil A. Lengade ,  Collin Howder ,  Dheeraj Kumar ,  Andrew L. Li

IPC: H01L27/11582 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L27/11556

Abstract: Microelectronic devices include a region with a tiered stack that includes insulative, conductive, and non-conductive structures arranged in tiers. The insulative structures vertically alternate with both the conductive and the non-conductive structures. Each of the conductive structures is vertically spaced from another of the conductive structures by at least one of the non-conductive structures and at least two of the insulative structures. A composition of the non-conductive structures differs from a composition of the insulative structures. In methods of fabrication, a precursor stack is formed to include the insulative structures vertically alternating with first and second non-conductive structures. In a region of the precursor stack, the first non-conductive structures are removed, forming voids between multi-structure tier groups. Conductive structures are formed in the voids. Electronic systems are also disclosed.

公开(公告)号：US20230387229A1

公开(公告)日：2023-11-30

申请号：US17804530

申请日：2022-05-27

Applicant: Micron Technology, Inc.

Inventor： Everett A. McTeer ,  Farrell M. Good ,  John M. Meldrim ,  Jordan D. Greenlee ,  Justin D. Shepherdson ,  Naiming Liu ,  Yifen Liu

IPC: H01L29/423 ,  H01L21/28 ,  H01L27/11582

CPC classification number: H01L29/4234 ,  H01L29/40117 ,  H01L27/11582

Abstract: A microelectronic device comprises conductive structures and insulative structures vertically alternating with the conductive structures. At least one of the insulative structures includes interfacial regions extending inward from vertical boundaries of the at least one of the insulative structures, and central region vertically interposed between the interfacial regions. The interfacial regions are doped with one or more of carbon and boron. The insulative structures comprise a lower concentration of the one or more of carbon and boron than the interfacial regions. Additional microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US11751396B2

公开(公告)日：2023-09-05

申请号：US17648528

申请日：2022-01-20

Applicant: Micron Technology, Inc.

Inventor： Yifen Liu ,  Tecla Ghilardi ,  George Matamis ,  Justin D. Shepherdson ,  Nancy M. Lomeli ,  Chet E. Carter ,  Erik R. Byers

IPC: H10B43/27 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53257 ,  H01L23/53271 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: A microelectronic device comprises a first set of tiers, each tier of the first set of tiers comprising alternating levels of a conductive material and an insulative material and having a first tier pitch, a second set of tiers adjacent to the first set of tiers, each tier of the second set of tiers comprising alternating levels of the conductive material and the insulative material and having a second tier pitch less than the first tier pitch, a third set of tiers adjacent to the second set of tiers, each tier of the third set of tiers comprising alternating levels of the conductive material and the insulative material and having a third tier pitch less than the second tier pitch, and a string of memory cells extending through the first set of tiers, the second set of tiers, and the third set of tiers. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US20220139958A1

公开(公告)日：2022-05-05

申请号：US17648528

申请日：2022-01-20

Applicant: Micron Technology, Inc.

Inventor： Yifen Liu ,  Tecla Ghilardi ,  George Matamis ,  Justin D. Shepherdson ,  Nancy M. Lomeli ,  Chet E. Carter ,  Erik R. Byers

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

Abstract: A microelectronic device comprises a first set of tiers, each tier of the first set of tiers comprising alternating levels of a conductive material and an insulative material and having a first tier pitch, a second set of tiers adjacent to the first set of tiers, each tier of the second set of tiers comprising alternating levels of the conductive material and the insulative material and having a second tier pitch less than the first tier pitch, a third set of tiers adjacent to the second set of tiers, each tier of the third set of tiers comprising alternating levels of the conductive material and the insulative material and having a third tier pitch less than the second tier pitch, and a string of memory cells extending through the first set of tiers, the second set of tiers, and the third set of tiers. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US11264404B2

公开(公告)日：2022-03-01

申请号：US16904317

申请日：2020-06-17

Applicant: Micron Technology, Inc.

Inventor： Yifen Liu ,  Tecla Ghilardi ,  George Matamis ,  Justin D. Shepherdson ,  Nancy M. Lomeli ,  Chet E. Carter ,  Erik R. Byers

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

Abstract: A microelectronic device comprises a first set of tiers, each tier of the first set of tiers comprising alternating levels of a conductive material and an insulative material and having a first tier pitch, a second set of tiers adjacent to the first set of tiers, each tier of the second set of tiers comprising alternating levels of the conductive material and the insulative material and having a second tier pitch less than the first tier pitch, a third set of tiers adjacent to the second set of tiers, each tier of the third set of tiers comprising alternating levels of the conductive material and the insulative material and having a third tier pitch less than the second tier pitch, and a string of memory cells extending through the first set of tiers, the second set of tiers, and the third set of tiers. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US20210343624A1

公开(公告)日：2021-11-04

申请号：US17367990

申请日：2021-07-06

Applicant: Micron Technology, Inc.

Inventor： Indra V. Chary ,  Chet E. Carter ,  Anilkumar Chandolu ,  Justin B. Dorhout ,  Jun Fang ,  Matthew J. King ,  Brett D. Lowe ,  Matthew Park ,  Justin D. Shepherdson

IPC: H01L23/48 ,  H01L21/033 ,  H01L27/11565 ,  H01L21/768 ,  H01L21/28 ,  H01L21/311 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11519

Abstract: A method used in forming a memory array and conductive through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. A mask is formed comprising horizontally-elongated trench openings and operative TAV openings above the stack. Etching is conducted of unmasked portions of the stack through the trench and operative TAV openings in the mask to form horizontally-elongated trench openings in the stack and to form operative TAV openings in the stack. Conductive material is formed in the operative TAV openings in the stack to form individual operative TAVs in individual of the operative TAV openings in the stack. A wordline-intervening structure is formed in individual of the trench openings in the stack.