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公开(公告)号：US20180114647A1
公开(公告)日：2018-04-26
申请号：US15849850
申请日：2017-12-21
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Noriyuki Inoue , Kazuo Hattori , Hiromasa Saeki
Abstract: A capacitor having an element main body including a metal high specific surface area substrate which has fine pores formed therein and a large specific surface area; a dielectric layer formed in a prescribed region on the surface of the high specific surface area substrate including the inner surfaces of the pores; and a conductive part on the dielectric layer. A first terminal electrode is electrically connected to the high specific surface area substrate. A second terminal electrode is electrically connected to the conductive part. The dielectric layer is interposed between the conductive part and the high specific surface area substrate, and the high specific surface area substrate and the second terminal electrode are electrically insulated from each other.
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公开(公告)号：US20160322171A1
公开(公告)日：2016-11-03
申请号：US15209128
申请日：2016-07-13
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Hiromasa Saeki , Noriyuki Inoue , Takeo Arakawa , Naoki lwaji
CPC classification number: H01G9/07 , H01G9/0029 , H01G9/0032 , H01G9/032 , H01G9/04 , H01G9/045 , H01G9/052 , H01G9/055 , H01G9/15
Abstract: A capacitor that includes a porous metal base material, a first buffer layer formed by an atomic layer deposition method on the porous metal base material, a dielectric layer formed by an atomic layer deposition method on the first buffer layer, and an upper electrode formed on the dielectric layer.
Abstract translation: 一种电容器，包括多孔金属基材，通过原子层沉积法在多孔金属基材上形成的第一缓冲层，在第一缓冲层上通过原子层沉积法形成的电介质层和形成在第一缓冲层上的上电极 电介质层。
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公开(公告)号：US10546691B2
公开(公告)日：2020-01-28
申请号：US15888351
申请日：2018-02-05
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Noriyuki Inoue , Takeo Arakawa , Kensuke Aoki , Hiromasa Saeki , Koichi Kanryo , Akihiro Tsuru , Haruhiko Mori
Abstract: A capacitor that includes a conductive base material with high specific surface area, a dielectric layer covering the conductive base material with high specific surface area, and an upper electrode covering the dielectric layer, in which the conductive base material with high specific surface area is formed of a metal sintered body as a whole.
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公开(公告)号：US20190074347A1
公开(公告)日：2019-03-07
申请号：US16176506
申请日：2018-10-31
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Tatsuya Funaki , Noriyuki Inoue
Abstract: A wafer level package which includes an IC chip; a rewiring layer on the IC chip; and a capacitor embedded in the rewiring layer.
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公开(公告)号：US10204744B2
公开(公告)日：2019-02-12
申请号：US15363336
申请日：2016-11-29
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Takeo Arakawa , Hiromasa Saeki , Noriyuki Inoue , Naoki Iwaji
Abstract: A capacitor that includes a porous metallic base material; a phosphorus-containing layer on the porous metallic base material; a dielectric layer on the phosphorus-containing layer; and an electrode on the dielectric layer.
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Patent Agency Ranking
公开(公告)号：US20180158611A1
公开(公告)日：2018-06-07
申请号：US15888389
申请日：2018-02-05
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Takeo Arakawa , Noriyuki Inoue , Hiromasa Saeki , Naoki Iwaji
Abstract: A capacitor that includes a conductive porous base material having a porous portion; a dielectric layer on the porous portion; and an upper electrode on the dielectric layer. In the porous portion of the conductive porous base material, a portion having a base material thickness between pores of 1.2 times or less of a thickness of the dielectric layer exits in 5% or more of the entire porous portion, and the dielectric layer is formed from a compound including atoms having an origin different from an origin of the conductive porous base material.
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公开(公告)号：US20180151297A1
公开(公告)日：2018-05-31
申请号：US15864534
申请日：2018-01-08
Applicant: Murata Manufacturing Co., Ltd.
Inventor： KAZUO HATTORI , Noriyuki Inoue , Hiromasa Saeki , Kensuke Aoki , Ken Ito
CPC classification number: H01G4/12 , H01G4/005 , H01G4/33 , H01G4/38 , H01G9/012 , H01G9/0425 , H01G9/045 , H01G9/055 , H01G9/07 , H01G9/15
Abstract: A capacitor having a conductive porous substrate with at least two electrostatic capacitance forming sections, each of the at least two electrostatic capacitance forming sections including a porous portion of the conductive porous substrate, a dielectric layer on the porous portion, and an upper electrode on the dielectric layer. The at least two electrostatic capacitance forming sections are electrically connected in series by the conductive porous substrate.
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公开(公告)号：US20180132356A1
公开(公告)日：2018-05-10
申请号：US15846492
申请日：2017-12-19
Applicant: Murata Manufacturing Co., Ltd.
Inventor： TATSUYA FUNAKI , Noriyuki Inoue
CPC classification number: H05K1/185 , H01G2/06 , H01G4/005 , H01G4/10 , H01G4/228 , H01G4/248 , H01G4/33 , H05K3/022 , H05K3/32 , H05K3/4602 , H05K2201/10015 , H05K2201/10522 , H05K2201/10537 , H05K2201/10553 , H05K2201/1056
Abstract: A method for manufacturing a capacitor built-in substrate includes: preparing a capacitor built-in core insulating film and laminating a respective buildup layer to each of opposed main surfaces of the capacitor built-in core insulating film. The capacitor built-in core insulating film includes a first and second metal layers, an insulating layer and a capacitor. The first and second metal layers are disposed so as to face each other with the insulating layer interposed therebetween. The capacitor is disposed so as to extend through the insulating layer with one capacitor electrode being electrically connected to the first metal layer and the other capacitor electrode being electrically connected to the second metal layer.
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公开(公告)号：US09536664B2
公开(公告)日：2017-01-03
申请号：US14045863
申请日：2013-10-04
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Noriyuki Inoue , Mayuko Nishihara , Makito Nakano , Masayoshi Shimizu
CPC classification number: H01G4/005 , H01G2/065 , H01G4/0085 , H01G4/232 , H01G4/30
Abstract: In an electronic component, capacitor conductors include linear portions parallel or substantially parallel to a lower surface of a laminate, and lead-out portions led out respectively from the linear portions to the lower surface. Outer electrodes are disposed on the lower surface and cover exposed portions where the lead-out portions are exposed at the lower surface, respectively. At least one of the linear portions includes a groove, which is recessed in a direction away from the lower surface, in a region thereof overlapping with the corresponding outer electrode when looking at the electronic component in a plan view from a z-axis direction.
Abstract translation: 在电子部件中，电容器导体包括平行于或基本上平行于层叠体的下表面的直线部分，以及分别从直线部分引导到下表面的引出部分。 外电极设置在下表面上，并分别覆盖引出部分在下表面露出的暴露部分。 直线部分中的至少一个在从z轴方向的平面图中观察电子部件时，在与相应的外部电极重叠的区域中包括沿远离下表面的方向凹陷的凹槽。
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公开(公告)号：US20190355516A1
公开(公告)日：2019-11-21
申请号：US16527170
申请日：2019-07-31
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Takehito Ishihara , Noriyuki Inoue , Tatsuya Funaki
Abstract: A capacitor is provided that includes an electrostatic capacitance forming portion with a first electrode/dielectric layer/second electrode structure, and a silicon portion. Moreover, the silicon portion is disposed on at least a part of a side of the electrostatic capacitance forming portion. When the capacitor is viewed in a thickness direction thereof, a region occupied by the silicon portion in a lower portion of the electrostatic capacitance forming portion is 50% or less.
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