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    PCIE TRAFFIC TRACKING HARDWARE IN A UNIFIED VIRTUAL MEMORY SYSTEM
    13.
    发明申请
    PCIE TRAFFIC TRACKING HARDWARE IN A UNIFIED VIRTUAL MEMORY SYSTEM 审中-公开

    公开(公告)号：US20190340145A1

    公开(公告)日：2019-11-07

    申请号：US16450830

    申请日：2019-06-24

    Applicant: NVIDIA CORPORATION

    Inventor： Jerome F. DULUK, JR. ,  Cameron BUSCHARDT ,  James Leroy DEMING ,  Brian FAHS ,  Mark HAIRGROVE ,  John MASHEY

    IPC: G06F13/40 ,  G06F12/123

    Abstract: Techniques are disclosed for tracking memory page accesses in a unified virtual memory system. An access tracking unit detects a memory page access generated by a first processor for accessing a memory page in a memory system of a second processor. The access tracking unit determines whether a cache memory includes an entry for the memory page. If so, then the access tracking unit increments an associated access counter. Otherwise, the access tracking unit attempts to find an unused entry in the cache memory that is available for allocation. If so, then the access tracking unit associates the second entry with the memory page, and sets an access counter associated with the second entry to an initial value. Otherwise, the access tracking unit selects a valid entry in the cache memory; clears an associated valid bit; associates the entry with the memory page; and initializes an associated access counter.

    MICROCONTROLLER FOR MEMORY MANAGEMENT UNIT
    15.
    发明申请
    MICROCONTROLLER FOR MEMORY MANAGEMENT UNIT 有权
    内存管理单元的微控制器

    公开(公告)号：US20140281356A1

    公开(公告)日：2014-09-18

    申请号：US14011655

    申请日：2013-08-27

    Applicant: NVIDIA CORPORATION

    Inventor： Cameron BUSCHARDT ,  Jerome F. DULUK, JR. ,  John MASHEY ,  Mark HAIRGROVE ,  James Leroy DEMING ,  Brian FAHS

    IPC: G06F12/10

    CPC classification number: G06F12/1009 ,  G06F2212/301

    Abstract: One embodiment of the present invention includes a microcontroller coupled to a memory management unit (MMU). The MMU is coupled to a page table included in a physical memory, and the microcontroller is configured to perform one or more virtual memory operations associated with the physical memory and the page table. In operation, the microcontroller receives a page fault generated by the MMU in response to an invalid memory access via a virtual memory address. To remedy such a page fault, the microcontroller performs actions to map the virtual memory address to an appropriate location in the physical memory. By contrast, in prior-art systems, a fault handler would typically remedy the page fault. Advantageously, because the microcontroller executes these tasks locally with respect to the MMU and the physical memory, latency associated with remedying page faults may be decreased. Consequently, overall system performance may be increased.

    Abstract translation: 本发明的一个实施例包括耦合到存储器管理单元（MMU）的微控制器。 MMU耦合到包括在物理存储器中的页表，并且微控制器被配置为执行与物理存储器和页表相关联的一个或多个虚拟存储器操作。 在操作中，微控制器响应于通过虚拟存储器地址的无效存储器访问而接收由MMU产生的页面错误。 为了纠正这种页面错误，微控制器执行操作以将虚拟存储器地址映射到物理存储器中的适当位置。 相比之下，在现有技术的系统中，故障处理器通常会补救页面错误。 有利地，由于微控制器相对于MMU和物理存储器在本地执行这些任务，所以与补救页错误相关联的延迟可能会降低。 因此，整体系统性能可能会增加。

    REPLAYING MEMORY TRANSACTIONS WHILE RESOLVING MEMORY ACCESS FAULTS
    16.
    发明申请
    REPLAYING MEMORY TRANSACTIONS WHILE RESOLVING MEMORY ACCESS FAULTS 有权
    在解决存储器访问错误时重新进行内存交易

    公开(公告)号：US20140281263A1

    公开(公告)日：2014-09-18

    申请号：US14109678

    申请日：2013-12-17

    Applicant: NVIDIA CORPORATION

    Inventor： James Leroy DEMING ,  Jerome F. DULUK, Jr. ,  John MASHEY ,  Mark HAIRGROVE ,  Lucien DUNNING ,  Jonathon Stuart Ramsay EVANS ,  Samuel H. DUNCAN ,  Cameron BUSCHARDT ,  Brian FAHS

    IPC: G06F12/10 ,  G06F12/08 ,  G06F12/12

    CPC classification number: G06F12/1027 ,  G06F9/467 ,  G06F12/08 ,  G06F2212/301 ,  G06F2212/684

    Abstract: One embodiment of the present invention is a parallel processing unit (PPU) that includes one or more streaming multiprocessors (SMs) and implements a replay unit per SM. Upon detecting a page fault associated with a memory transaction issued by a particular SM, the corresponding replay unit causes the SM, but not any unaffected SMs, to cease issuing new memory transactions. The replay unit then stores the faulting memory transaction and any faulting in-flight memory transaction in a replay buffer. As page faults are resolved, the replay unit replays the memory transactions in the replay buffer—removing successful memory transactions from the replay buffer—until all of the stored memory transactions have successfully executed. Advantageously, the overall performance of the PPU is improved compared to conventional PPUs that, upon detecting a page fault, stop performing memory transactions across all SMs included in the PPU until the fault is resolved.

    Abstract translation: 本发明的一个实施例是包括一个或多个流式多处理器（SM）并且实现每SM的重放单元的并行处理单元（PPU）。 当检测到与由特定SM发出的存储器事务相关联的页面错误时，相应的重放单元使得SM，而不是任何未受影响的SM停止发行新的存储器事务。 重播单元然后将故障存储器事务和任何故障的飞行中存储器事务存储在重放缓冲器中。 当页面错误得到解决时，重播单元重播重播缓冲区中的内存事务，从重播缓冲区中移除成功的内存事务，直到所有存储的内存事务都已成功执行。 有利的是，与常规PPU相比，PPU的整体性能得到改善，在常规PPU检测到页面故障之后，停止执行包含在PPU中的所有SM的存储器事务，直到故障被解决为止。

    EFFICIENT MEMORY VIRTUALIZATION IN MULTI-THREADED PROCESSING UNITS
    18.
    发明申请
    EFFICIENT MEMORY VIRTUALIZATION IN MULTI-THREADED PROCESSING UNITS 审中-公开
    多线程处理单元的高效内存虚拟化

    公开(公告)号：US20140122829A1

    公开(公告)日：2014-05-01

    申请号：US13660815

    申请日：2012-10-25

    Applicant: NVIDIA CORPORATION

    Inventor： Nick BARROW-WILLIAMS ,  Brian FAHS ,  Jerome F. DULUK, JR. ,  James Leroy DEMING ,  Timothy John PURCELL ,  Lucien DUNNING ,  Mark HAIRGROVE

    IPC: G06F12/10

    CPC classification number: G06F12/08 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/684

    Abstract: A technique for simultaneously executing multiple tasks, each having an independent virtual address space, involves assigning an address space identifier (ASID) to each task and constructing each virtual memory access request to include both a virtual address and the ASID. During virtual to physical address translation, the ASID selects a corresponding page table, which includes virtual to physical address mappings for the ASID and associated task. Entries for a translation look-aside buffer (TLB) include both the virtual address and ASID to complete each mapping to a physical address. Deep scheduling of tasks sharing a virtual address space may be implemented to improve cache affinity for both TLB and data caches.

    Abstract translation: 一种用于同时执行多个任务的技术，每个任务具有独立的虚拟地址空间，包括为每个任务分配地址空间标识符（ASID），并且构建每个虚拟存储器访问请求以包括虚拟地址和ASID。 在虚拟到物理地址转换期间，ASID选择相应的页表，其中包括ASID和相关任务的虚拟到物理地址映射。 翻译后备缓冲区（TLB）的条目包括虚拟地址和ASID，以完成对物理地址的每个映射。 可以实现对共享虚拟地址空间的任务的深度调度，以提高对TLB和数据高速缓存的高速缓存亲和性。

    MICROCONTROLLER FOR MEMORY MANAGEMENT UNIT
    20.
    发明申请
    MICROCONTROLLER FOR MEMORY MANAGEMENT UNIT 审中-公开

    公开(公告)号：US20170371802A9

    公开(公告)日：2017-12-28

    申请号：US14011643

    申请日：2013-08-27

    Applicant: NVIDIA CORPORATION

    Inventor： Cameron BUSCHARDT ,  Jerome F. DULUK, JR. ,  John MASHEY ,  Mark HAIRGROVE ,  James Leroy DEMING ,  Brian FAHS

    IPC: G06F12/1009

    CPC classification number: G06F12/1009 ,  G06F2212/301

    Abstract: One embodiment of the present invention includes a microcontroller coupled to a memory management unit (MMU). The MMU is coupled to a page table included in a physical memory, and the microcontroller is configured to perform one or more virtual memory operations associated with the physical memory and the page table. In operation, the microcontroller receives a page fault generated by the MMU in response to an invalid memory access via a virtual memory address. To remedy such a page fault, the microcontroller performs actions to map the virtual memory address to an appropriate location in the physical memory. By contrast, in prior-art systems, a fault handler would typically remedy the page fault. Advantageously, because the microcontroller executes these tasks locally with respect to the MMU and the physical memory, latency associated with remedying page faults may be decreased. Consequently, overall system performance may be increased.

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