公开(公告)号：US11750949B2

公开(公告)日：2023-09-05

申请号：US17465184

申请日：2021-09-02

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Charles Qingle Wu ,  Yanying He ,  Weiyi Zhang

IPC: H04N25/71 ,  H03L7/08 ,  H01L27/02 ,  H04N25/772

CPC classification number: H04N25/745 ,  H01L27/0251 ,  H03L7/08 ,  H04N25/772

Abstract: Reference clock CMOS input buffer with self-calibration and improved ESD performance. In one embodiment, a reference clock input buffer of an image sensor includes a Schmitt trigger configured to generate a clock signal having a falling edge and a rising edge. The falling edge and the rising edge are separated by a hysteresis voltage. The Schmitt trigger includes a plurality of output switches and a plurality of voltage control switches that are individually coupled to individual output switches [M2-i] of the plurality of output switches. Voltage of the falling edge signal or the rising edge signal of the Schmitt trigger is adjustable by selectively switching at least one voltage control switch of the plurality of voltage control switches.

公开(公告)号：US11184196B1

公开(公告)日：2021-11-23

申请号：US17125605

申请日：2020-12-17

Applicant: OmniVision Technologies, Inc.

Inventor： Li Yang ,  Charles Qingle Wu ,  Nan Liu

IPC: H04L25/02 ,  H04L25/08

Abstract: A digital differential line receiver includes a differential signal to single-ended conversion amplifier coupled to receive a data line and data-complement line of a differential signal; a first termination resistor coupled to the data line of the differential signal; a second termination resistor coupled to the data-complement line of the differential signal; a first impedance-adjusting transistor coupled between the first termination resistor and a common mode line; a second impedance-adjusting transistor coupled between the second termination resistor and the common mode line; a control-voltage generator coupled to sense the common mode line and provide a control voltage, the control voltage generator configured to adjust the control voltage to a voltage level such that a combined impedance of the first termination resistor, the first impedance-adjusting transistor, the second termination resistor, and the second impedance-adjusting transistor matches a specified impedance.

公开(公告)号：US09762833B1

公开(公告)日：2017-09-12

申请号：US15163582

申请日：2016-05-24

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Charles Qingle Wu ,  Yun Hak Koh

IPC: H04N5/374 ,  H03K19/00 ,  H03K19/003

CPC classification number: H04N5/3741 ,  H03K19/00315 ,  H04N5/376

Abstract: Techniques and methods for reducing or preventing latch up in row decoder circuits are disclosed herein. An example apparatus may include an array of pixels, a row address decoder, and control circuitry. The row decode circuit including a plurality of decode circuits, each including at least two transistors having respective body terminals coupled to a first node. The control circuitry including a body biasing circuit coupled to the first node, the body biasing circuit to adaptively provide a bias voltage to the first node in response to an operating state of the imaging system and/or a change in one of two reference voltages based on a control signal provided by a bias control circuit.

公开(公告)号：US20230062619A1

公开(公告)日：2023-03-02

申请号：US17465184

申请日：2021-09-02

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Charles Qingle Wu ,  Yanying He ,  Weiyi Zhang

IPC: H04N5/376 ,  H01L27/02 ,  H04N5/3745 ,  H03L7/08

Abstract: Reference clock CMOS input buffer with self-calibration and improved ESD performance. In one embodiment, a reference clock input buffer of an image sensor includes a Schmitt trigger configured to generate a clock signal having a falling edge and a rising edge. The falling edge and the rising edge are separated by a hysteresis voltage. The Schmitt trigger includes a plurality of output switches and a plurality of voltage control switches that are individually coupled to individual output switches [M2-i] of the plurality of output switches. Voltage of the falling edge signal or the rising edge signal of the Schmitt trigger is adjustable by selectively switching at least one voltage control switch of the plurality of voltage control switches.

公开(公告)号：US10298382B2

公开(公告)日：2019-05-21

申请号：US15673298

申请日：2017-08-09

Applicant: OmniVision Technologies, Inc.

Inventor： Charles Qingle Wu ,  Qi Niu

IPC: H04L7/033 ,  H04L7/08 ,  G11B20/14 ,  H03L7/099 ,  H03L7/085 ,  G06F7/68 ,  G06F1/08 ,  H03C3/09 ,  H03L7/18

Abstract: A frequency divider unit has a digital frequency divider configured to divide by an odd integer, and a dual-edge-triggered one-shot coupled to double frequency of an output of the digital frequency divider. The frequency divider unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, and 3.5. In embodiments, the frequency divider unit relies on circuit delays to determine an output pulsewidth, and in other embodiments the output pulsewidth is determined from a clock signal. In embodiments, the unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, 3.5, 4.5, 5.5, 6.5, and 7.5 as well as many integer ratios including 2, 4, 6, and 8. In embodiments, the digital frequency divider is configurable to provide a 50% duty cycle to the one-shot.

公开(公告)号：US09735950B1

公开(公告)日：2017-08-15

申请号：US15296344

申请日：2016-10-18

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Min Liu ,  Zhizhong Xie ,  Charles Qingle Wu

IPC: H04L7/00

CPC classification number: H04L7/0087 ,  G06F13/40 ,  H04L7/0331 ,  H04L25/49

Abstract: An example burst mode clock data recovery circuit may include a clock recovery circuit coupled to receive a plurality of data signals, and provide a recovered clock signal in response. Each of the plurality of data signals includes data and an embedded clock signal, and the plurality of data signals may be based on an encoded symbol. The clock recovery circuit is coupled to generate the recovered clock signal in response to a first one of the plurality of data signals. A data recovery circuit may be coupled to receive the plurality of data signals and the recovered clock signal, and provide a plurality of recovered data signals in response to the recovered clock signal. The data recover circuit is coupled to delay each of the plurality of data signals, and capture each of the delayed plurality of data signals in response to the at least one clock pulse.

公开(公告)号：US09355054B2

公开(公告)日：2016-05-31

申请号：US14149430

申请日：2014-01-07

Applicant: OmniVision Technologies, Inc.

Inventor： Charles Qingle Wu ,  Min Liu

IPC: G06F1/08 ,  G06F13/40 ,  G06F1/10 ,  G11C7/10 ,  G11C29/02 ,  H04L7/00 ,  H04L7/033

CPC classification number: G06F13/40 ,  G06F1/10 ,  G11C7/1066 ,  G11C7/1093 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0041 ,  H04L7/033

Abstract: A Mobile Industry Processor Interface (MIPI) physical layer (D-PHY) serial communication link and a method of reducing clock-data skew in a MIPI D-PHY serial communication link include apparatus including a clock transmitting circuit for transmitting a clock signal on a first lane of the MIPI D-PHY serial link, a data transmitting circuit for transmitting a data signal on a second lane of the MIPI D-PHY serial link, a clock receiving circuit for receiving the clock signal on the first lane of the MIPI D-PHY serial link, and a data receiving circuit for receiving the data signal on the second lane of the MIPI D-PHY serial link. The clock transmitting circuit and the data transmitting circuit transmit the clock signal and the data signal in phase during a calibration mode and out of phase during a normal operation mode.

Abstract translation: 移动工业处理器接口（MIPI）物理层（D-PHY）串行通信链路和减少MIPI D-PHY串行通信链路中的时钟数据偏移的方法包括：设备，其包括时钟发送电路，用于在 MIPI D-PHY串行链路的第一通道，用于在MIPI D-PHY串行链路的第二通道上发送数据信号的数据发送电路，用于在MIPI D的第一通道上接收时钟信号的时钟接收电路 -PHY串行链路，以及用于在MIPI D-PHY串行链路的第二通道上接收数据信号的数据接收电路。 时钟发送电路和数据发送电路在正常操作模式期间在校准模式期间同相地发送时钟信号和数据信号。

公开(公告)号：US09300331B2

公开(公告)日：2016-03-29

申请号：US13673856

申请日：2012-11-09

Applicant: OmniVision Technologies, Inc.

Inventor： Min Liu ,  Yun Hak Koh ,  Charles Qingle Wu

IPC: H04B1/04 ,  H04N9/00 ,  H04L25/02 ,  G09G5/00

CPC classification number: H04B1/04 ,  G09G5/006 ,  G09G2310/0289 ,  G09G2370/08 ,  H04L25/02 ,  H04L25/0272 ,  H04L25/0286 ,  H04N9/00

Abstract: A transmitter for generating a differential signal pair including a pre-emphasis component. In an embodiment, the transmitter comprises pre-driver circuitry including an input to receive a single-ended data signal. The differential transmitter further comprises a load circuit coupled between the input and a node coupled to an output of the pre-driver circuitry which corresponds to a constituent signal of the differential signal pair. In another embodiment, the load circuit is configurable to provide a signal path between the input and the node. A configuration of the load circuit allows for a type of pre-emphasis to be included in the constituent signal.

Abstract translation: 一种用于产生包括预加重分量的差分信号对的发射机。 在一个实施例中，发射机包括预驱动器电路，其包括用于接收单端数据信号的输入。 差分发射器还包括耦合在输入端和耦合到预驱动器电路的输出端的节点之间的负载电路，其对应于差分信号对的构成信号。 在另一个实施例中，负载电路可配置为在输入和节点之间提供信号路径。 负载电路的配置允许将一种预加重包括在组成信号中。