公开(公告)号：US09673786B2

公开(公告)日：2017-06-06

申请号：US13862015

申请日：2013-04-12

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi Rasouli ,  Animesh Datta ,  Jay Madhukar Shah ,  Martin Saint-Laurent ,  Peeyush Kumar Parkar ,  Sachin Bapat ,  Ramaprasath Vilangudipitchai ,  Mohamed Hassan Abu-Rahma ,  Prayag Bhanubhai Patel

IPC: H03K3/02 ,  H03K3/289 ,  H03K19/00 ,  H03K3/012 ,  H03K3/356 ,  H03K3/3562

CPC classification number: H03K3/012 ,  H03K3/356008 ,  H03K3/35625

Abstract: A circuit including a logic gate responsive to a clock signal and to a control signal. The circuit also includes a master stage of a flip-flop. The circuit further includes a slave stage of the flip-flop responsive to the master stage. The circuit further includes an inverter responsive to the logic gate and configured to output a delayed version of the clock signal. An output of the logic gate and the delayed version of the clock signal are provided to the master stage and to the slave stage of the flip-flop. The master stage is responsive to the control signal to control the slave stage.

公开(公告)号：US09070552B1

公开(公告)日：2015-06-30

申请号：US14267888

申请日：2014-05-01

Applicant: QUALCOMM Incorporated

Inventor： Jay Madhukar Shah ,  Kamesh Medisetti ,  Vijayalakshmi Ranganna ,  Animesh Datta

IPC: H01L23/52 ,  H01L27/02 ,  H01L23/528

CPC classification number: H01L27/0207 ,  H01L23/5286 ,  H01L27/11807 ,  H01L2027/11881 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A standard cell CMOS device includes a first power rail extending across the standard cell. The first power rail is connected to one of a first voltage or a second voltage less than the first voltage. The device further includes a second power rail extending across the standard cell. The second power rail is connected to an other one of the first voltage or the second voltage. The second power rail includes a metal x layer interconnect and a set of metal x−1 layer interconnects connected to the metal x layer interconnect. The device further includes a set of CMOS transistor devices between the first and second power rails and powered by the first and second power rails. The device further includes an x−1 layer interconnect extending under and orthogonal to the second power rail. The x−1 layer interconnect is coupled to the set of CMOS transistor devices.

Abstract translation: 标准单元CMOS器件包括跨标准单元延伸的第一电源轨。 第一电源轨连接到小于第一电压的第一电压或第二电压之一。 该装置还包括延伸穿过标准单元的第二电力轨道。 第二电源轨连接到第一电压或第二电压中的另一个。 第二电源轨包括金属x层互连和连接到金属x层互连的一组金属x-1层互连。 该器件还包括在第一和第二电源轨之间的一组CMOS晶体管器件，并由第一和第二电源轨提供动力。 该装置还包括延伸在第二电力轨下并正交于第二电力轨道的x-1层互连。 x-1层互连耦合到该组CMOS晶体管器件。

公开(公告)号：US09024658B2

公开(公告)日：2015-05-05

申请号：US13905060

申请日：2013-05-29

Applicant: QUALCOMM Incorporated

Inventor： Jay Madhukar Shah ,  Chethan Swamynathan ,  Animesh Datta

IPC: H03K19/02 ,  G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/318541

Abstract: Techniques for reducing scan overhead in a scannable flop tray are described herein. In one embodiment, a scan circuit for a flop tray comprises a tri-state circuit configured to invert an input data signal and output the inverted data signal to an input of a flip-flop of the flop tray in a normal mode, and to block the data signal from the input of the flip-flop in a scan mode. The scan circuit also comprises a pass gate configured to pass a scan signal to the input of the flip-flop in the scan mode, and to block the scan signal from the input of the flip-flop in the normal mode.

Abstract translation: 本文描述了用于减少可扫描的翻转托盘中的扫描开销的技术。 在一个实施例中，用于翻转托盘的扫描电路包括三态电路，其被配置为反转输入数据信号，并将反相数据信号以正常模式输出到翻转托盘的触发器的输入，并阻塞 来自触发器的输入的扫描模式的数据信号。 扫描电路还包括一个通道门，其被配置为在扫描模式下将扫描信号传递到触发器的输入，并且在正常模式下阻止来自触发器的输入的扫描信号。

公开(公告)号：US20140330994A1

公开(公告)日：2014-11-06

申请号：US13887846

申请日：2013-05-06

Applicant: QUALCOMM INCORPORATED

Inventor： Lalan J. Mishra ,  Dexter T. Chun ,  Animesh Datta

IPC: G06F13/42

CPC classification number: G06F13/42 ,  G06F13/1689 ,  G06F13/4234 ,  G06F13/4243 ,  G06F13/4282 ,  G11C7/10 ,  G11C7/222 ,  H04L7/0008 ,  H04L7/0037 ,  H04L25/4902

Abstract: A synchronous data-link throughput enhancement technique based on data signal duty-cycle and phase modulation demodulation is disclosed. A method includes receiving multiple bits to be transmitted, encoding the multiple bits to generate a multi-bit signal that represents the multiple bits, and transmitting, via a synchronous interface, the multi-bit signal during a time period that corresponds to one-half of a cycle of a synchronization signal.

Abstract translation: 公开了一种基于数据信号占空比和相位调制解调的同步数据链路吞吐量增强技术。 一种方法包括接收要发送的多个比特，对多个比特进行编码以产生表示多个比特的多比特信号，并且在对应于一半的时间段期间经由同步接口发送多比特信号 的同步信号的周期。

公开(公告)号：US20140225655A1

公开(公告)日：2014-08-14

申请号：US13767729

申请日：2013-02-14

Applicant: QUALCOMM INCORPORATED

Inventor： Seid Hadi Rasouli ,  Animesh Datta ,  Ohsang Kwon

IPC: H03L7/00

CPC classification number: H04L7/0331 ,  H03K5/135 ,  H04L7/0276

Abstract: Techniques for clock gating a synchronizer are described herein. In one embodiment a circuit for clock gating a synchronizer comprises a clock-gating circuit configured to receive an input clock signal, and to selectively provide either the input clock signal or a fixed clock signal to the synchronizer. The circuit also comprises a comparator configured to compare a data value of a data signal input to the synchronizer, a first value of the synchronizer, and a second value of the synchronizer with one another, to instruct the clock-gating circuit to provide the input clock signal to the synchronizer if the data value, the first value, and the second value are not all the same, and to instruct the clock-gating circuit to provide the fixed clock signal to the synchronizer if the data value, the first value, and the second value are all the same.

Abstract translation: 本文描述了用于时钟门控同步器的技术。 在一个实施例中，用于时钟门控同步器的电路包括配置成接收输入时钟信号并且选择性地向同步器提供输入时钟信号或固定时钟信号的时钟门控电路。 该电路还包括比较器，其被配置为将输入到同步器的数据信号的数据值，同步器的第一值和同步器的第二值彼此进行比较，以指示时钟门控电路提供输入 如果所述数据值，所述第一值和所述第二值不完全相同，则指示所述同步器的时钟信号，并且指示所述时钟选通电路向所述同步器提供所述固定时钟信号，如果所述数据值，所述第一值， 而第二个值都是一样的。

公开(公告)号：US11508725B2

公开(公告)日：2022-11-22

申请号：US16777639

申请日：2020-01-30

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi Rasouli ,  Michael Joseph Brunolli ,  Christine Sung-An Hau-Riege ,  Mickael Malabry ,  Sucheta Kumar Harish ,  Prathiba Balasubramanian ,  Kamesh Medisetti ,  Nikolay Bomshtein ,  Animesh Datta ,  Ohsang Kwon

IPC: H01L27/092 ,  H01L23/482 ,  H01L27/02 ,  H01L23/528 ,  H01L21/8238 ,  H01L23/522 ,  H03K17/16 ,  H03K17/687

Abstract: A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect and a second interconnect. The first interconnect is on an interconnect level extending in a length direction to connect the PMOS drains together, and the second interconnect is on the interconnect level extending in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level physically couple the first interconnect and the second interconnect to an output of the CMOS device. A third interconnect on the interconnect level extends perpendicular to the length direction and offset from the set of interconnects. The third interconnect is capable of flowing current from the PMOS drains or from the NMOS drains to the output of the CMOS device.

公开(公告)号：US09972624B2

公开(公告)日：2018-05-15

申请号：US13975185

申请日：2013-08-23

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi Rasouli ,  Michael Joseph Brunolli ,  Christine Sung-An Hau-Riege ,  Mickael Malabry ,  Sucheta Kumar Harish ,  Prathiba Balasubramanian ,  Kamesh Medisetti ,  Nikolay Bomshtein ,  Animesh Datta ,  Ohsang Kwon

IPC: H01L27/092 ,  H01L21/8238 ,  H03K17/16 ,  H03K17/687 ,  H01L23/482 ,  H01L27/02 ,  H01L23/522

CPC classification number: H01L27/0921 ,  H01L21/823871 ,  H01L23/4824 ,  H01L23/522 ,  H01L27/0207 ,  H01L27/092 ,  H01L2924/0002 ,  H03K17/168 ,  H03K17/6872 ,  H01L2924/00

Abstract: A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect on an interconnect level extending in a length direction to connect the PMOS drains together. A second interconnect on the interconnect level extends in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level couple the first interconnect and the second interconnect together. A third interconnect on the interconnect level extends perpendicular to the length direction and is offset from the set of interconnects to connect the first interconnect and the second interconnect together.

公开(公告)号：US09786663B2

公开(公告)日：2017-10-10

申请号：US13975074

申请日：2013-08-23

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi Rasouli ,  Animesh Datta ,  Ohsang Kwon

IPC: H01L27/092 ,  H01L21/8238 ,  H01L23/482 ,  H01L27/02 ,  H03K17/16 ,  H03K17/687 ,  H01L23/522

CPC classification number: H01L27/0921 ,  H01L21/823871 ,  H01L23/4824 ,  H01L23/522 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/092 ,  H01L2924/0002 ,  H03K17/168 ,  H03K17/6872 ,  H01L2924/00

Abstract: A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together through at least one other interconnect level.

公开(公告)号：US09584121B2

公开(公告)日：2017-02-28

申请号：US14736213

申请日：2015-06-10

Applicant: QUALCOMM Incorporated

Inventor： Qi Ye ,  Zhengyu Duan ,  Steven James Dillen ,  Animesh Datta

IPC: H03K3/289 ,  H03K19/00 ,  H03K3/3562

CPC classification number: H03K19/0013 ,  G01R31/318541 ,  G06F1/04 ,  H03K3/037 ,  H03K3/35625

Abstract: A MOS device includes a first latch configured with one latch feedback F and configured to receive a latch input I and a latch clock C. The first latch is configured to output Q, where the output Q is a function of CF, IF, and IC, and the latch feedback F is a function of the output Q. The first latch may include a first set of transistors stacked in series in which the first set of transistors includes at least five transistors. The MOS device may further include a second latch coupled to the first latch. The second latch may be configured as a latch in a scan mode and as a pulse latch in a functional mode. The first latch may operate as a master latch and the second latch may operate as a slave latch during the scan mode.

Abstract translation: MOS器件包括配置有一个锁存器反馈F并被配置为接收锁存器输入I和锁存时钟C的第一锁存器。第一锁存器被配置为输出Q，其中输出Q是CF，IF和IC的函数 并且锁存反馈F是输出Q的函数。第一锁存器可以包括串联堆叠的第一组晶体管，其中第一组晶体管包括至少五个晶体管。 MOS器件还可以包括耦合到第一锁存器的第二锁存器。 第二锁存器可以被配置为扫描模式下的锁存器和功能模式中的脉冲锁存器。 第一锁存器可以作为主锁存器操作，并且第二锁存器可以在扫描模式期间作为从锁存器操作。

公开(公告)号：US09564881B2

公开(公告)日：2017-02-07

申请号：US14720634

申请日：2015-05-22

Applicant: QUALCOMM Incorporated

Inventor： Qi Ye ,  Steven James Dillen ,  Animesh Datta ,  Zhengyu Duan ,  Satyanarayana Sahu ,  Praveen Narendranath

IPC: H03K3/012 ,  H03K3/037 ,  H03K5/131 ,  H03K5/13

CPC classification number: H03K3/0375 ,  H03K3/012 ,  H03K3/037 ,  H03K5/131

Abstract: A pulse generator includes a latch module for storing first/second states, a pulse clock module for generating a clock pulse, and a delay module for delaying the clock pulse at a second latch-module input. The latch module has a first latch-module input coupled to a clock, the second latch-module input, and a latch-module output. The pulse clock module has a first pulse-clock-module input coupled to the clock, a second pulse-clock-module input coupled to the latch-module output, and a pulse-clock-module output. The delay module is coupled between the latch-module output and second pulse-clock-module input or between the pulse-clock-module output and second latch-module input. The delay module provides functionally I1IA at a delay module output, where I1 is a function of I and IA is a function of IN0 and B0, and where I is a delay module input, B0 is a first input bit, and IN0 is a first net input.

Abstract translation: 脉冲发生器包括用于存储第一/第二状态的锁存模块，用于产生时钟脉冲的脉冲时钟模块以及用于在第二锁存模块输入端延迟时钟脉冲的延迟模块。 锁存模块具有耦合到时钟的第一锁存模块输入端，第二锁存模块输入端和锁存模块输出端。 脉冲时钟模块具有耦合到时钟的第一脉冲时钟模块输入，耦合到锁存模块输出的第二脉冲时钟模块输入和脉冲时钟模块输出。 延迟模块耦合在锁存模块输出和第二个脉冲时钟模块输入之间，或者连接在脉冲时钟模块输出和第二个锁存模块输入之间。 延迟模块在延迟模块输出端提供功能上的I1IA，其中I1是I的函数，IA是IN0和B0的函数，其中I是延迟模块输入，B0是第一个输入位，IN0是第一个 净输入。