公开(公告)号：US20170169902A1

公开(公告)日：2017-06-15

申请号：US14970273

申请日：2015-12-15

Applicant: QUALCOMM INCORPORATED

Inventor： DEXTER TAMIO CHUN ,  Yanru Li

IPC: G11C29/42 ,  G06F11/10 ,  G06F12/02 ,  G06F13/24 ,  G11C7/10 ,  G06F12/08

CPC classification number: G11C29/42 ,  G06F11/1016 ,  G06F11/1048 ,  G06F11/1064 ,  G06F11/1072 ,  G06F12/0246 ,  G06F12/0875 ,  G06F13/24 ,  G11C7/1072

Abstract: Systems, methods, and computer programs are disclosed for resolving dynamic random access memory (DRAM) defects. One embodiment is a system comprising a dynamic random access memory (DRAM) system electrically coupled to a system on chip (SoC). The SoC comprises a cache and a cache controller. The cache controller is configured to store corrected data for a failed physical codeword address associated with the DRAM in the cache and provide further access to the failed physical codeword address from the cache instead of the DRAM system.

公开(公告)号：US20170109090A1

公开(公告)日：2017-04-20

申请号：US14885797

申请日：2015-10-16

Applicant: QUALCOMM INCORPORATED

Inventor： DEXTER TAMIO CHUN ,  YANRU LI ,  ALEXANDER GANTMAN

IPC: G06F3/06 ,  G06F12/10 ,  G06F12/06

CPC classification number: G06F3/0625 ,  G06F3/064 ,  G06F3/0673 ,  G06F12/0292 ,  G06F12/0607 ,  G06F12/1009 ,  G06F2212/1028 ,  G06F2212/20 ,  G06F2212/65 ,  Y02D10/13

Abstract: Systems and methods are disclosed for providing memory channel interleaving with selective power or performance optimization. One such method comprises configuring a memory address map for two or more memory devices accessed via two or more respective memory channels. The memory address map comprises one or more interleaved blocks and a plurality of linear blocks. Each interleaved block comprises an interleaved address space for relatively higher performance tasks, and each linear block comprises a linear address space for relatively lower power tasks. A request is received from a process for a virtual memory page. The request comprises a preference for power savings or performance. If the preference is for power savings, the virtual memory page is mapped to a physical page in a concatenated linear block.

公开(公告)号：US20170004034A1

公开(公告)日：2017-01-05

申请号：US14791352

申请日：2015-07-03

Applicant: QUALCOMM INCORPORATED

Inventor： RICHARD ALAN STEWART ,  DEXTER TAMIO CHUN

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1044 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/1068 ,  G06F11/1072 ,  G06F12/0246

Abstract: Systems, methods, and computer programs are disclosed for providing error detection or correction with flash cell mapping. One embodiment is a method comprising generating raw page data for a physical page in a main array of a flash memory device. The raw page data comprises less than a capacity of the physical page generated using a non-power-of-two flash cell mapping. One or more parity bits are generated for the raw page data using an error detection or correction scheme. The method stores the raw page data and the one or more parity bits in the physical page in the main array.

Abstract translation: 公开了用于提供具有闪存单元映射的错误检测或校正的系统，方法和计算机程序。 一个实施例是一种方法，包括为闪存设备的主阵列中的物理页生成原始页数据。 原始页数据包括使用非二功能闪存单元映射生成的物理页面的容量小于该容量。 使用错误检测或校正方案为原始页数据生成一个或多个奇偶校验位。 该方法将原始页面数据和一个或多个奇偶校验位存储在主阵列中的物理页面中。

公开(公告)号：US20160320994A1

公开(公告)日：2016-11-03

申请号：US14699431

申请日：2015-04-29

Applicant: QUALCOMM INCORPORATED

Inventor： DEXTER TAMIO CHUN ,  YANRU LI

IPC: G06F3/06 ,  G06F9/44

CPC classification number: G06F3/0625 ,  G06F3/0659 ,  G06F3/068 ,  G06F9/4403 ,  G06F12/0238 ,  G06F12/0638 ,  G06F2212/1028 ,  G06F2212/205 ,  G06F2212/7204 ,  Y02D10/13

Abstract: Systems, methods, and computer programs are disclosed for providing a heterogeneous system memory in a portable communication device. One system comprises a system on chip (SoC) coupled to a nonvolatile random access memory (NVRAM) and a volatile random access memory (VRAM). The SoC comprises an operating system for mapping a heterogeneous system memory comprising the NVRAM and the VRAM. The operating system comprises a memory manager configured to allocate a first portion of the NVRAM as a block device for a swap operation, a second portion of the NVRAM for program code and read-only data, and a third portion of the NVRAM for operating system page tables. The VRAM is allocated for a program heap and a program stack.

Abstract translation: 公开了用于在便携通信设备中提供异构系统存储器的系统，方法和计算机程序。 一个系统包括耦合到非易失性随机存取存储器（NVRAM）和易失性随机存取存储器（VRAM）的片上系统（SoC）。 SoC包括用于映射包括NVRAM和VRAM的异构系统存储器的操作系统。 操作系统包括存储器管理器，其被配置为将NVRAM的第一部分分配为用于交换操作的块设备，用于程序代码和只读数据的NVRAM的第二部分以及用于操作系统的NVRAM的第三部分 页表。 VRAM被分配给程序堆和程序堆栈。

公开(公告)号：US20150293822A1

公开(公告)日：2015-10-15

申请号：US14253770

申请日：2014-04-15

Applicant: QUALCOMM INCORPORATED

Inventor： DEXTER TAMIO CHUN ,  YANRU LI ,  JUNG PILL KIM ,  DEEPTI VIJAYALAKSHMI SRIRAMAGIRI

IPC: G06F11/20 ,  G06F11/14

CPC classification number: G06F11/2017 ,  G06F3/0688 ,  G06F11/0772 ,  G06F11/08 ,  G06F11/1008 ,  G06F11/1016 ,  G06F11/1048 ,  G06F11/1417 ,  G06F2201/85 ,  G06F2212/1032 ,  G06F2212/7201 ,  G11C29/00 ,  G11C29/08 ,  G11C29/52 ,  G11C29/70

Abstract: Systems, methods, and computer programs are disclosed for recovering from dynamic random access memory (DRAM) defects. One method comprises determining that an uncorrected bit error has occurred for a physical codeword address associated with a dynamic random access memory (DRAM) device coupled to a system on chip (SoC). A kernel page associated with a DRAM page comprising the physical codeword address is identified as a bad page. Recovery from the uncorrected bit error is provided by rebooting a system comprising the SoC and the DRAM device. In response to the rebooting, the identified kernel page is excluded from being allocated for DRAM operation.

Abstract translation: 公开了用于从动态随机存取存储器（DRAM）缺陷中恢复的系统，方法和计算机程序。 一种方法包括确定与耦合到片上系统（SoC）的动态随机存取存储器（DRAM）设备相关联的物理码字地址已经发生未校正的位错误。 与包括物理码字地址的DRAM页面相关联的内核页面被识别为坏页面。 通过重新启动包括SoC和DRAM设备的系统来提供从未校正的位错误的恢复。 响应于重新启动，识别的内核页面被排除在为DRAM操作分配之前。

公开(公告)号：US20180335798A1

公开(公告)日：2018-11-22

申请号：US15601924

申请日：2017-05-22

Applicant: QUALCOMM Incorporated

Inventor： DEXTER TAMIO CHUN ,  Richard Alan Stewart

IPC: G06F1/08 ,  G06F3/06 ,  G06F1/32

CPC classification number: G06F1/08 ,  G06F1/324 ,  G06F1/3275 ,  G06F3/0611 ,  G06F3/0629 ,  G06F3/0683 ,  G06F13/1689

Abstract: Pipelined logic latency in a memory system operating at a reduced frequency may be compensated for. Pipelined logic may be controlled using at least first and second clock signals. All registers of the pipelined logic may be controlled using the first clock signal when the memory system is operating at a higher frequency. However, when the memory system is operating at a reduced frequency, one or more registers may be controlled using the first clock signal, and one or more other registers may be controlled using the second clock signal.

公开(公告)号：US20170220412A1

公开(公告)日：2017-08-03

申请号：US15489621

申请日：2017-04-17

Applicant: QUALCOMM INCORPORATED

Inventor： RICHARD ALAN STEWART ,  DEXTER TAMIO CHUN

IPC: G06F11/10 ,  G06F3/06 ,  G06F12/02

CPC classification number: G06F11/1044 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/1068 ,  G06F11/1072 ,  G06F12/0246

Abstract: Systems, methods, and computer programs are disclosed for providing error detection or correction with flash cell mapping. One embodiment is a method comprising generating raw page data for a physical page in a main array of a flash memory device. The raw page data comprises less than a capacity of the physical page generated using a non-power-of-two flash cell mapping. One or more parity bits are generated for the raw page data using an error detection or correction scheme. The method stores the raw page data and the one or more parity bits in the physical page in the main array.

公开(公告)号：US20170199814A1

公开(公告)日：2017-07-13

申请号：US14993045

申请日：2016-01-11

Applicant: QUALCOMM INCORPORATED

Inventor： STEPHEN MOLLOY ,  DEXTER TAMIO CHUN

IPC: G06F12/06 ,  G06F12/08

CPC classification number: G06F12/0638 ,  G06F12/0804 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0868 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/0893 ,  G06F2212/1032 ,  G06F2212/205 ,  G06F2212/214 ,  G06F2212/281 ,  G06F2212/3042 ,  G06F2212/305

Abstract: Systems, methods, and computer programs are disclosed for providing non-volatile system memory with volatile memory program caching. One such method comprises storing an executable program in a non-volatile random access memory. In response to an initial launch of the executable program, the executable program is loaded from the non-volatile random access memory into a volatile memory cache for execution. In response to an initial suspension of the executable program, cache pages corresponding to the executable program are flushed into the non-volatile random access memory.

公开(公告)号：US20170177497A1

公开(公告)日：2017-06-22

申请号：US14976537

申请日：2015-12-21

Applicant: QUALCOMM INCORPORATED

Inventor： DEXTER TAMIO CHUN ,  HYUNSUK SHIN

IPC: G06F12/10 ,  G06F12/08

CPC classification number: G06F12/1009 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/1081 ,  G06F2212/1024 ,  G06F2212/401 ,  G06F2212/70 ,  G06F2212/7201

Abstract: Systems and methods are disclosed for providing logical-to-physical address translation for a managed NAND flash storage device. One embodiment is a system comprising a system on chip (SoC) electrically coupled to a volatile memory device. A direct memory access (DMA) controller is electrically coupled to the SoC. The DMA controller receives a logical address to be translated to a physical address associated with a managed NAND flash storage device. A cache controller is configured to fetch from the volatile memory device a portion of a logical-to-physical (L2P) address table comprising a compressed version of a L2P mapping for the logical address. A compression block is configured to decompress the compressed version of the L2P mapping to determine the physical address corresponding to the logical address.

公开(公告)号：US20170108911A1

公开(公告)日：2017-04-20

申请号：US14885793

申请日：2015-10-16

Applicant: QUALCOMM INCORPORATED

Inventor： DEXTER TAMIO CHUN ,  YANRU LI

IPC: G06F1/32 ,  G06F12/10

CPC classification number: G06F1/324 ,  G06F1/3275 ,  G06F3/0625 ,  G06F12/0607 ,  G06F12/10 ,  G06F12/1009 ,  G06F2212/1016 ,  G06F2212/1028 ,  Y02D10/13

Abstract: Systems and methods are disclosed for providing memory channel interleaving with selective power or performance optimization. One such method comprises configuring a memory address map for two or more memory devices accessed via two or more respective memory channels with an interleaved region and a linear region. The interleaved region comprises an interleaved address space for relatively higher performance tasks. The linear region comprises a linear address space for relatively lower power tasks. A request is received from a process for a virtual memory page. The request comprises a preference for power savings or performance. The virtual memory page is assigned to a free physical page in the linear region or the interleaved region according to the preference for power savings or performance.