公开(公告)号：US20160172299A1

公开(公告)日：2016-06-16

申请号：US14610876

申请日：2015-01-30

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Noveski ,  Milind Pravin Shah ,  Rajneesh Kumar

IPC: H01L23/528 ,  H01L23/31 ,  H01L23/00 ,  H01L23/522 ,  H01L23/498

CPC classification number: H01L23/5283 ,  H01L23/3157 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0348 ,  H01L2224/03602 ,  H01L2224/03914 ,  H01L2224/05546 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/1111 ,  H01L2224/11334 ,  H01L2224/11438 ,  H01L2224/13007 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16014 ,  H01L2224/16111 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/2711 ,  H01L2224/27438 ,  H01L2224/29006 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81101 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2924/2064 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: An integrated device package that includes a die, a substrate, a fill and a conductive interconnect. The die includes a pillar, where the pillar has a first pillar width. The substrate (e.g., package substrate, interposer) includes a dielectric layer and a substrate interconnect (e.g., surface interconnect, embedded interconnect). The fill is located between the die and the substrate. The conductive interconnect is located within the fill. The conductive interconnect includes a first interconnect width that is about the same or less than the first pillar width. The conductive interconnect is coupled to the pillar and the substrate interconnect. The fill is a non-conductive photosensitive material. The fill is a photosensitive film. The substrate interconnect includes a second interconnect width that is equal or greater than the first pillar width. The conductive interconnect includes one of at least a paste, a solder and/or an enhanced solder comprising a polymeric material.

Abstract translation: 一种集成器件封装，其包括管芯，衬底，填充物和导电互连。 模具包括支柱，其中柱具有第一柱宽度。 衬底（例如，封装衬底，插入器）包括电介质层和衬底互连（例如，表面互连，嵌入式互连）。 填充物位于管芯和衬底之间。 导电互连位于填充物内。 导电互连包括大约等于或小于第一柱宽度的第一互连宽度。 导电互连耦合到柱和衬底互连。 填充物是非导电感光材料。 填充物是感光膜。 衬底互连包括等于或大于第一柱宽度的第二互连宽度。 导电互连包括至少一种包含聚合材料的糊状物，焊料和/或增强焊料中的至少一种。

公开(公告)号：US20150221528A9

公开(公告)日：2015-08-06

申请号：US14255349

申请日：2014-04-17

Applicant: QUALCOMM INCORPORATED

Inventor： Omar James Bchir ,  Milind Pravin Shah ,  Sashidhar Movva

IPC: H01L21/56 ,  H01L23/00

CPC classification number: H01L21/563 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/562 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/92125 ,  H01L2924/01057 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A backside mold configuration (BSMC) process for manufacturing packaged integrated circuits includes applying a mold compound to a side of a packaging substrate opposite an attached die. The mold compound is deposited on a dielectric (such as photo resist). The mold compound and dielectric are patterned after coupling a die to the packaging substrate to expose a contact pad of the packaging substrate. After patterning the mold compound and dielectric, a packaging connection is coupled to contact pads through the mold compound and dielectric. The mold compound surrounding the packaging connection reduces warpage of the packaging substrate during processing. Additionally, patterning the dielectric after attaching the die improves reliability of the packaging connection.

Abstract translation: 用于制造封装集成电路的背面模具配置（BSMC）工艺包括将模具化合物施加到与附接模具相对的封装基板的一侧。 将模具化合物沉积在电介质（例如光致抗蚀剂）上。 在将模具连接到包装基板上以暴露包装基板的接触垫之后，模制化合物和电介质被图案化。 在模制化合物和电介质图案化之后，封装连接通过模具化合物和电介质耦合到接触垫。 围绕包装连接的模具化合物减少处理期间包装基材的翘曲。 此外，在连接芯片之后对电介质进行图案化提高了封装连接的可靠性。

公开(公告)号：US20150179590A1

公开(公告)日：2015-06-25

申请号：US14251518

申请日：2014-04-11

Applicant: QUALCOMM Incorporated

Inventor： Jie Fu ,  Manuel Aldrete ,  Milind Pravin Shah

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L24/03 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/0903 ,  H01L2224/0912 ,  H01L2924/12042 ,  H01L2924/381 ,  H01L2924/00

Abstract: Some novel features pertain to an integrated device that includes a substrate, a first via, and a first bump pad. The first via traverses the substrate. The first via has a first via dimension. The first bump pad is on a surface of the substrate. The first bump pad is coupled to the first via. The first bump pad has a first pad dimension that is equal or less then the first via dimension. In some implementations, the integrated device includes a second via and a second bump pad. The second via traverses the substrate. The second via has a second via dimension. The second bump pad is on the surface of the substrate. The second bump pad is coupled to the second via. The second bump pad has a second pad dimension that is equal or less then the second via dimension.

Abstract translation: 一些新颖的特征涉及包括基板，第一通孔和第一凸块焊盘的集成装置。 第一个通孔穿过基板。 第一个通孔具有第一通孔尺寸。 第一凸块焊盘位于基板的表面上。 第一碰撞焊盘耦合到第一通孔。 第一凸块焊盘具有等于或小于第一通孔尺寸的第一焊盘尺寸。 在一些实施方案中，集成器件包括第二通孔和第二凸点焊盘。 第二个通孔穿过基板。 第二通孔具有第二通孔尺寸。 第二凸点焊盘位于基板的表面上。 第二凸点焊盘耦合到第二通孔。 第二凸块焊盘具有等于或小于第二通孔尺寸的第二焊盘尺寸。

公开(公告)号：US20140264946A1

公开(公告)日：2014-09-18

申请号：US13833921

申请日：2013-03-15

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan Kim ,  Omar James Bchir ,  Milind Pravin Shah ,  Marcus Bernard Hsu ,  David Fraser Rae

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: To achieve a package-on-package having an advantageously reduced height, a first package substrate has a window sized to receive a second package die. The first package substrate interconnects to the second package substrate through a plurality of package-to-package interconnects such that the first and second substrates are separated by a gap. The second package die has a thickness greater than the gap such that the second package die is at least partially disposed within the first package substrate's window.

Abstract translation: 为了实现具有有利地降低的高度的封装封装，第一封装衬底具有尺寸适于接收第二封装管芯的窗口。 第一封装衬底通过多个封装到封装互连而互连到第二封装衬底，使得第一和第二衬底被间隙隔开。 第二封装管芯具有大于间隙的厚度，使得第二封装管芯至少部分地设置在第一封装衬底的窗口内。