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    EMBEDDED BRIDGE STRUCTURE IN A SUBSTRATE
    3.
    发明申请
    EMBEDDED BRIDGE STRUCTURE IN A SUBSTRATE 有权
    嵌入桥梁结构在基板上

    公开(公告)号：US20150116965A1

    公开(公告)日：2015-04-30

    申请号：US14067677

    申请日：2013-10-30

    Applicant: Qualcomm Incorporated

    Inventor： Chin-Kwan Kim ,  Omar James Bchir ,  Dong Wook Kim ,  Hong Bok We

    IPC: H05K1/18 ,  H05K1/11

    CPC classification number: H05K1/18 ,  H01L23/5383 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/15192 ,  H01L2924/15313 ,  H05K1/11 ,  H01L2924/014

    Abstract: Some novel features pertain to a substrate that includes a first dielectric layer and a bridge structure. The bridge structure is embedded in the first dielectric layer. The bridge structure is configured to provide an electrical connection between a first die and a second die. The first and second dies are configured to be coupled to the substrate. The bridge structure includes a first set of interconnects and a second dielectric layer. The first set of interconnects is embedded in the first dielectric layer. In some implementations, the bridge structure further includes a second set of interconnects. In some implementations, the second dielectric layer is embedded in the first dielectric layer. The some implementations, the first dielectric layer includes the first set of interconnects of the bridge structure, a second set of interconnects in the bridge structure, and a set of pads in the bridge structure.

    Abstract translation: 一些新颖的特征涉及包括第一介电层和桥结构的基板。 桥结构嵌入在第一电介质层中。 桥结构构造成在第一管芯和第二管芯之间提供电连接。 第一和第二管芯被配置为耦合到衬底。 桥结构包括第一组互连和第二介电层。 第一组互连嵌入在第一介质层中。 在一些实现中，桥结构还包括第二组互连。 在一些实施方案中，第二介电层被嵌入在第一介电层中。 在一些实施方式中，第一介电层包括桥结构的第一组互连，桥结构中的第二组互连以及桥结构中的一组焊盘。

    Package substrate with testing pads on fine pitch traces
    4.
    发明授权
    Package substrate with testing pads on fine pitch traces 有权
    封装衬底，测试垫在细间距迹线上

    公开(公告)号：US09370097B2

    公开(公告)日：2016-06-14

    申请号：US13783168

    申请日：2013-03-01

    Applicant: QUALCOMM Incorporated

    Inventor： Chin-Kwan Kim ,  Kuiwon Kang ,  Omar James Bchir

    IPC: H05K7/10 ,  H05K1/11 ,  G01R31/28 ,  H05K1/02 ,  H05K3/34

    CPC classification number: H05K1/111 ,  G01R31/2818 ,  H05K1/0268 ,  H05K3/3452 ,  H05K2201/10674 ,  Y10T29/49004 ,  Y10T29/49124 ,  Y10T29/4913

    Abstract: Some implementations provide a substrate that includes several traces, a solder resist layer covering the several traces, and a testing pad coupled to a trace from the several traces. The testing pad is at least partially exposed and at least partially free of the solder resist layer when a chip is coupled to the substrate. In some implementations, the several traces have a pitch that is 100 microns (μm) or less. In some implementations, the substrate is a package substrate. In some implementations, the package substrate is a package substrate on which a thermal compression flip chip is mounted during an assembly process. In some implementations, the testing pad is free of a direct connection with a bonding component of the chip when the chip is coupled to the substrate. In some implementations, the bonding component is one of a solder ball.

    Abstract translation: 一些实施方案提供了包括几条迹线的衬底，覆盖几条迹线的阻焊层，以及耦合到几条迹线的迹线的测试焊盘。 当芯片耦合到衬底时，测试焊盘至少部分地暴露并且至少部分地不含阻焊层。 在一些实施方案中，多个迹线具有100微米（μm）或更小的间距。 在一些实施方式中，衬底是封装衬底。 在一些实施方案中，封装衬底是在组装过程期间安装热压缩倒装芯片的封装衬底。 在一些实施方案中，当芯片耦合到衬底时，测试焊盘不与芯片的焊接部件直接连接。 在一些实施方式中，接合部件是焊球之一。

    Ultra fine pitch and spacing interconnects for substrate
    7.
    发明授权
    Ultra fine pitch and spacing interconnects for substrate 有权
    用于衬底的超细间距和间距互连

    公开(公告)号：US08772951B1

    公开(公告)日：2014-07-08

    申请号：US14014192

    申请日：2013-08-29

    Applicant: QUALCOMM Incorporated

    Inventor： Chin-Kwan Kim ,  Rajneesh Kumar ,  Omar James Bchir

    IPC: H01L21/4763 ,  H01L29/40

    CPC classification number: H01L23/498 ,  H01L21/4857 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/11 ,  H01L2224/14133 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17051 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81801 ,  H05K1/0296 ,  H05K1/111 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/09227

    Abstract: Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect embedded in a first surface of the first dielectric layer, and a second interconnect on the first surface of the first dielectric layer. The first interconnect is offset from the first surface of the first dielectric layer. The first interconnect being offset towards an inner portion of the first dielectric layer. In some implementations, the substrate further includes a third interconnect embedded in the first surface of the first dielectric layer, and a fourth interconnect on the first surface of the first dielectric layer. The first interconnect and the second interconnect are adjacent interconnects. In some implementations, the substrate further includes a first pad on the first surface of the first dielectric layer. The first pad is coupled to the first interconnect.

    Abstract translation: 一些新颖的特征涉及包括第一介电层，嵌入在第一介电层的第一表面中的第一互连以及在第一介电层的第一表面上的第二互连的衬底。 第一互连件与第一介电层的第一表面偏移。 第一互连件朝向第一介电层的内部部分偏移。 在一些实施方案中，衬底还包括嵌入在第一介电层的第一表面中的第三互连和在第一介电层的第一表面上的第四互连。 第一互连和第二互连是相邻的互连。 在一些实施方案中，衬底还包括在第一介电层的第一表面上的第一焊盘。 第一焊盘耦合到第一互连。

    PACKAGE SUBSTRATE COMPRISING SURFACE INTERCONNECT AND CAVITY COMPRISING ELECTROLESS FILL
    9.
    发明申请
    PACKAGE SUBSTRATE COMPRISING SURFACE INTERCONNECT AND CAVITY COMPRISING ELECTROLESS FILL 有权
    包含表面互连和包含电镀膜的孔的包装基底

    公开(公告)号：US20150296616A1

    公开(公告)日：2015-10-15

    申请号：US14251486

    申请日：2014-04-11

    Applicant: QUALCOMM Incorporated

    Inventor： Houssam Wafic Jomaa ,  Omar James Bchir ,  Chin-Kwan Kim

    IPC: H05K1/11 ,  H05K3/42 ,  H05K1/02

    CPC classification number: H05K1/112 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0298 ,  H05K3/422 ,  H05K3/425 ,  H05K3/429 ,  H05K2201/0344 ,  H05K2201/09036 ,  H05K2201/10378

    Abstract: Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect, a first cavity, and a first electroless metal layer. The first dielectric layer includes a first surface and a second surface. The first interconnect is on the first surface of the substrate layer. The first cavity traverses the first surface of the first dielectric layer. The first electroless metal layer is formed at least partially in the first cavity. The first electroless metal layer defines a second interconnect embedded in the first dielectric layer. In some implementations, the substrate further includes a core layer. The core layer includes a first surface and a second surface. The first surface of the core layer is coupled to the second surface of the first dielectric layer. In some implementations, the substrate further includes a second dielectric layer.

    Abstract translation: 一些新颖特征涉及包括第一介电层，第一互连，第一空腔和第一无电金属层的基板。 第一电介质层包括第一表面和第二表面。 第一互连在衬底层的第一表面上。 第一空腔穿过第一介电层的第一表面。 第一无电金属层至少部分地形成在第一腔中。 第一无电金属层限定嵌入在第一介电层中的第二互连。 在一些实施方案中，衬底还包括芯层。 芯层包括第一表面和第二表面。 芯层的第一表面耦合到第一介电层的第二表面。 在一些实施方案中，衬底还包括第二介电层。

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