公开(公告)号：US09806063B2

公开(公告)日：2017-10-31

申请号：US14699863

申请日：2015-04-29

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan Kim ,  Rajneesh Kumar ,  Vladimir Noveski ,  Jie Fu ,  Ahmer Raza Syed ,  Milind Pravin Shah ,  Omar James Bchir

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/16 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L21/56 ,  H01L23/538

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Some features pertain to a package that includes a redistribution portion, a first die coupled to the redistribution portion, a core layer coupled to the redistribution portion, and an encapsulation layer encapsulating the first die and the core layer. The redistribution portion includes a first dielectric layer. The core layer has a higher Young's Modulus than the encapsulation layer. In some implementations, the core layer includes a glass fiber (e.g., core layer is a glass reinforced dielectric layer). In some implementations, the core layer has a Young's Modulus of about at least 15 gigapascals (Gpa). In some implementations, the first die includes a front side and a back side, where the front side of the first die is coupled to the redistribution portion. In some implementations, the first dielectric layer is a photo imageable dielectric (PID) layer.

公开(公告)号：US20160322332A1

公开(公告)日：2016-11-03

申请号：US14699863

申请日：2015-04-29

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan Kim ,  Rajneesh Kumar ,  Vladimir Noveski ,  Jie Fu ,  Ahmer Raza Syed ,  Milind Pravin Shah ,  Omar James Bchir

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/522 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Some features pertain to a package that includes a redistribution portion, a first die coupled to the redistribution portion, a core layer coupled to the redistribution portion, and an encapsulation layer encapsulating the first die and the core layer. The redistribution portion includes a first dielectric layer. The core layer has a higher Young's Modulus than the encapsulation layer. In some implementations, the core layer includes a glass fiber (e.g., core layer is a glass reinforced dielectric layer). In some implementations, the core layer has a Young's Modulus of about at least 15 gigapascals (Gpa). In some implementations, the first die includes a front side and a back side, where the front side of the first die is coupled to the redistribution portion. In some implementations, the first dielectric layer is a photo imageable dielectric (PID) layer.

Abstract translation: 一些特征涉及包括再分配部分，耦合到再分配部分的第一裸片，耦合到再分配部分的核心层以及封装第一裸片和核心层的封装层的封装。 再分配部分包括第一电介质层。 核心层具有比封装层更高的杨氏模量。 在一些实施方案中，芯层包括玻璃纤维（例如，芯层是玻璃增强介电层）。 在一些实施方案中，核心层具有约至少15吉帕斯卡（Gpa）的杨氏模量。 在一些实施方案中，第一管芯包括前侧和后侧，其中第一管芯的前侧连接到再分配部分。 在一些实施方案中，第一电介质层是可光致成像电介质（PID）层。

公开(公告)号：US20160172299A1

公开(公告)日：2016-06-16

申请号：US14610876

申请日：2015-01-30

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Noveski ,  Milind Pravin Shah ,  Rajneesh Kumar

IPC: H01L23/528 ,  H01L23/31 ,  H01L23/00 ,  H01L23/522 ,  H01L23/498

CPC classification number: H01L23/5283 ,  H01L23/3157 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0348 ,  H01L2224/03602 ,  H01L2224/03914 ,  H01L2224/05546 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/1111 ,  H01L2224/11334 ,  H01L2224/11438 ,  H01L2224/13007 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16014 ,  H01L2224/16111 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/2711 ,  H01L2224/27438 ,  H01L2224/29006 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81101 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2924/2064 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: An integrated device package that includes a die, a substrate, a fill and a conductive interconnect. The die includes a pillar, where the pillar has a first pillar width. The substrate (e.g., package substrate, interposer) includes a dielectric layer and a substrate interconnect (e.g., surface interconnect, embedded interconnect). The fill is located between the die and the substrate. The conductive interconnect is located within the fill. The conductive interconnect includes a first interconnect width that is about the same or less than the first pillar width. The conductive interconnect is coupled to the pillar and the substrate interconnect. The fill is a non-conductive photosensitive material. The fill is a photosensitive film. The substrate interconnect includes a second interconnect width that is equal or greater than the first pillar width. The conductive interconnect includes one of at least a paste, a solder and/or an enhanced solder comprising a polymeric material.

Abstract translation: 一种集成器件封装，其包括管芯，衬底，填充物和导电互连。 模具包括支柱，其中柱具有第一柱宽度。 衬底（例如，封装衬底，插入器）包括电介质层和衬底互连（例如，表面互连，嵌入式互连）。 填充物位于管芯和衬底之间。 导电互连位于填充物内。 导电互连包括大约等于或小于第一柱宽度的第一互连宽度。 导电互连耦合到柱和衬底互连。 填充物是非导电感光材料。 填充物是感光膜。 衬底互连包括等于或大于第一柱宽度的第二互连宽度。 导电互连包括至少一种包含聚合材料的糊状物，焊料和/或增强焊料中的至少一种。

公开(公告)号：US20160148864A1

公开(公告)日：2016-05-26

申请号：US14703617

申请日：2015-05-04

Applicant: QUALCOMM Incorporated

Inventor： Jie Fu ,  David Fraser Rae ,  Manuel Aldrete ,  Vladimir Noveski ,  Chin-Kwan Kim

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L24/92 ,  H01L23/49811 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/81801 ,  H01L2224/8385 ,  H01L2224/92225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/152

Abstract: Some features pertain to an integrated circuit device that includes a first package substrate, a first die coupled to the first package substrate, a second package substrate, and a solder joint structure coupled to the first package substrate and the second package substrate. The solder joint structure includes a solder comprising a first melting point temperature, and a conductive material comprising a second melting point temperature that is less than the first melting point temperature. In some implementations, the conductive material is one of at least a homogeneous material and/or a heterogeneous material. In some implementations, the conductive material includes a first electrically conductive material and a second material. The conductive material is an electrically conductive material.

Abstract translation: 一些特征涉及集成电路器件，其包括第一封装衬底，耦合到第一封装衬底的第一管芯，第二封装衬底以及耦合到第一封装衬底和第二封装衬底的焊点结构。 焊接结构包括包含第一熔点温度的焊料和包含小于第一熔点温度的第二熔点温度的导电材料。 在一些实施方案中，导电材料是至少均质材料和/或异质材料之一。 在一些实施方案中，导电材料包括第一导电材料和第二材料。 导电材料是导电材料。

公开(公告)号：US10037941B2

公开(公告)日：2018-07-31

申请号：US14610876

申请日：2015-01-30

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Noveski ,  Milind Pravin Shah ,  Rajneesh Kumar

IPC: H01L23/528 ,  H01L23/31 ,  H01L23/522 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/5283 ,  H01L23/3157 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0348 ,  H01L2224/03602 ,  H01L2224/03914 ,  H01L2224/05546 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/1111 ,  H01L2224/11334 ,  H01L2224/11438 ,  H01L2224/13007 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16111 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/2711 ,  H01L2224/27438 ,  H01L2224/29006 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81101 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2924/2064 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: An integrated device package that includes a die, a substrate, a fill and a conductive interconnect. The die includes a pillar, where the pillar has a first pillar width. The substrate (e.g., package substrate, interposer) includes a dielectric layer and a substrate interconnect (e.g., surface interconnect, embedded interconnect). The fill is located between the die and the substrate. The conductive interconnect is located within the fill. The conductive interconnect includes a first interconnect width that is about the same or less than the first pillar width. The conductive interconnect is coupled to the pillar and the substrate interconnect. The fill is a non-conductive photosensitive material. The fill is a photosensitive film. The substrate interconnect includes a second interconnect width that is equal or greater than the first pillar width. The conductive interconnect includes one of at least a paste, a solder and/or an enhanced solder comprising a polymeric material.