公开(公告)号：US10713136B2

公开(公告)日：2020-07-14

申请号：US15713557

申请日：2017-09-22

Applicant: QUALCOMM Incorporated

Inventor： Fahad Ahmed ,  Chulmin Jung ,  Sei Seung Yoon ,  Esin Terzioglu

IPC: G11C29/00 ,  G06F11/20 ,  G11C29/44 ,  G11C8/12

Abstract: In an example, a method of memory repair may include receiving, by a memory repair unit, a plurality of memory identifiers. The method may include determining, by the memory repair unit, that a first memory identifier of the plurality of memory identifiers corresponds to a first memory of a plurality of memories. The method may include determining, by the memory repair unit, that a second memory identifier corresponds to a second memory of the plurality of memories. The method may include outputting, by the memory repair unit, in parallel: a first value to a repair enable input of the first memory, and a second value to a repair enable input of the second memory.

公开(公告)号：US10133285B2

公开(公告)日：2018-11-20

申请号：US15791226

申请日：2017-10-23

Applicant: QUALCOMM Incorporated

Inventor： Sanjay Bhagawan Patil ,  Daniel Stasiak ,  Martin Pierre Saint-Laurent ,  Rui Li ,  Bin Liang ,  Sei Seung Yoon ,  Chulmin Jung

IPC: G05F1/10 ,  G06F1/32 ,  H02M1/32

Abstract: A computer-readable storage medium for controlling voltage droop storing instructions that, when executed by a processor, cause a device to perform operations including receiving a first voltage to a first input of a first component of a device. The first voltage corresponding to a first logical value causes a first internal power supply of the first component to be charged using an external power supply. The operations further include providing a second voltage to a second input of a second component of the device in response to a first voltage level of the first internal power supply satisfying a second voltage level. The second voltage corresponding to the first logical value causes a second internal power supply of the second component of the device to be charged using the external power supply.

公开(公告)号：US09941881B1

公开(公告)日：2018-04-10

申请号：US15467943

申请日：2017-03-23

Applicant: QUALCOMM Incorporated

Inventor： Changho Jung ,  Derek Yang ,  Sei Seung Yoon

IPC: H03K19/20 ,  H03K19/003 ,  H03K19/0948

CPC classification number: H03K19/00323 ,  H03K3/012 ,  H03K3/037 ,  H03K19/0948 ,  H03K19/20

Abstract: A latch circuit includes an AND-NOR gate, a NAND gate, and a NOR gate. The AND-NOR gate includes a first AND-input configured to receive input data and a second AND-input coupled to an output of the NAND gate. The AND-NOR gate includes a NOR-input coupled to an output of the NOR gate, and an output configured to generate output data. The NAND gate includes a first input coupled to the output of the AND-NOR gate and a second input configured to receive a clock signal. The NOR gate includes a first input coupled to the output of the AND-NOR gate and a second input configured to receive a complementary clock signal. During a first half clock cycle, the AND-NOR gate passes the data from the input to the output. During a second half clock cycle, the feedback configuration of the AND-NOR gate and the NOR gate latches the data.

公开(公告)号：US09940987B2

公开(公告)日：2018-04-10

申请号：US15070963

申请日：2016-03-15

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Po-Hung Chen ,  David Li ,  Sei Seung Yoon

IPC: G11C7/00 ,  G11C8/08 ,  G11C8/10 ,  G11C8/06 ,  G11C5/14

CPC classification number: G11C8/08 ,  G11C5/14 ,  G11C8/06 ,  G11C8/10

Abstract: A memory is provided that includes a row decoder that decodes an address into a plurality of decoded signals for selecting a word line to be asserted from a plurality of word lines. Each word line is driven through a decoder level-shifter that processes the decoded signals. Each decoder level-shifter corresponds to a unique combination of the decoded signals. The row decoder is in a logic power domain such that the decoded signals are asserted to a logic power supply voltage. When a decoder level-shifter's unique combination of decoded signals are asserted by the row decoder, the decoder level-shifter drives the corresponding word line with a memory power supply voltage for a memory power domain.

公开(公告)号：US09851730B2

公开(公告)日：2017-12-26

申请号：US14684128

申请日：2015-04-10

Applicant: QUALCOMM Incorporated

Inventor： Sanjay Bhagawan Patil ,  Daniel Stasiak ,  Martin Pierre Saint-Laurent ,  Rui Li ,  Bin Liang ,  Sei Seung Yoon ,  Chulmin Jung

IPC: G05F1/10 ,  G06F1/32 ,  H02M1/32

CPC classification number: G05F1/10 ,  G06F1/26 ,  G06F1/263 ,  G06F1/3287 ,  G06F1/329 ,  H02M1/32

Abstract: Voltage droop control is disclosed. A device includes a first component coupled to an external power supply and a second component coupled to the external power supply. The first component includes a first input configured to receive a first voltage, a first internal power supply configured to be charged by the external power supply in response to the first voltage corresponding to a first logical value, and a voltage droop controller configured to output a second voltage via a first output. The second voltage corresponds to the first logical value in response to a first voltage level of the first internal power supply satisfying a second voltage level. The second component includes a second input configured to receive the second voltage from the first output.

公开(公告)号：US09401201B1

公开(公告)日：2016-07-26

申请号：US14720383

申请日：2015-05-22

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Fahad Ahmed ,  David Li ,  Sei Seung Yoon

IPC: G11C11/41 ,  G11C11/419 ,  G11C5/14 ,  G11C11/413 ,  G11C16/10 ,  G11C16/06 ,  G11C7/12 ,  G11C7/10 ,  G11C13/00

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C5/143 ,  G11C5/147 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/12 ,  G11C11/413 ,  G11C13/0069 ,  G11C16/06 ,  G11C16/10

Abstract: A memory and a method for operating a memory are provided. The memory includes a memory cell configured to be powered from a first voltage source, a bitline, and a write driver configured to write to the memory cell through the bitline, the write driver comprising a pull-up circuit to pull up bitline voltage towards a second voltage source while using the first voltage source to limit the bitline voltage, the first and second voltage sources being in different voltage domains.

Abstract translation: 提供了一种用于操作存储器的存储器和方法。 存储器包括被配置为由第一电压源，位线和写入驱动器供电的存储器单元，配置为通过位线写入存储器单元，写入驱动器包括上拉电路，以将位线电压拉向 第二电压源，同时使用第一电压源来限制位线电压，第一和第二电压源处于不同的电压域。

公开(公告)号：US20160078965A1

公开(公告)日：2016-03-17

申请号：US14488171

申请日：2014-09-16

Applicant: Qualcomm Incorporated

Inventor： Venugopal Boynapalli ,  Kashyap Ramachandra Bellur ,  Prabaharan Balu ,  Bilal Zafar ,  Alex Dongkyu Park ,  Sei Seung Yoon

IPC: G11C29/08

CPC classification number: G11C29/08 ,  G11C8/16 ,  G11C29/20 ,  G11C29/32 ,  G11C2029/3202

Abstract: An example scannable register file includes a plurality of memory cells and, a shift phase of a scan test shifts data bits from a scan input through the plurality of memory cells to a scan output. The shifting can be performed by, on each clock cycle, reading one of the plurality of memory cells to supply the scan out and writing one of the plurality of memory cells with the data bit on a scan input. To perform sequential reads and writes on each clock cycle, the scannable register can generate a write clock that, during the shift phase, is inverted from the clock used for functional operation. The write clock is generated without glitches so that unintended writes do not occur. Scannable register files can be integrated with scan-based testing (e.g., using automatic test pattern generation) of other modules in an integrated circuit.

Abstract translation: 示例性可扫描寄存器文件包括多个存储器单元，并且扫描测试的移位阶段将数据位从通过多个存储器单元的扫描输入移位到扫描输出。 可以通过在每个时钟周期读取多个存储器单元中的一个以提供扫描输出并将多个存储器单元中的一个与扫描输入上的数据位一起写入来执行移位。 为了在每个时钟周期执行顺序读取和写入，可扫描寄存器可以产生一个写入时钟，在写入时钟期间，在移位阶段，与用于功能操作的时钟相反。 写时钟不产生毛刺，因此不会发生意外的写入。 可扫描寄存器文件可以集成在集成电路中的其他模块的基于扫描的测试（例如，使用自动测试模式生成）。

公开(公告)号：US20150279451A1

公开(公告)日：2015-10-01

申请号：US14227330

申请日：2014-03-27

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Wuyang Hao ,  Sei Seung Yoon

IPC: G11C11/418

CPC classification number: G11C11/418 ,  G11C8/08

Abstract: A pulse latch is provided that latches a ground signal responsive to decoded signal carried on a decoded signal node. The pulse latch includes a reset logic circuit that controls a switch coupled between the decoded signal node and ground such that when the switch is turned on by the reset logic circuit, the decoded signal node is grounded. The reset of the decoded signal node by the reset logic circuit is responsive to a ground signal. The ground signal is generated so as to be responsive to a clock edge. Thus, the reset of the decoded signal node is also responsive to the clock edge.

Abstract translation: 提供脉冲锁存器，其响应于解码信号节点上承载的解码信号而锁存接地信号。 脉冲锁存器包括复位逻辑电路，其控制耦合在解码信号节点和地之间的开关，使得当开关由复位逻辑电路导通时，解码信号节点接地。 复位逻辑电路对解码信号节点的复位响应于接地信号。 产生接地信号以响应于时钟沿。 因此，解码信号节点的复位也响应时钟边缘。

公开(公告)号：US09064556B2

公开(公告)日：2015-06-23

申请号：US14061528

申请日：2013-10-23

Applicant: QUALCOMM Incorporated

Inventor： Chirag Gulati ,  Lakshmikantha Holla Vakwadi ,  Sei Seung Yoon

IPC: G11C7/10 ,  G11C7/12

CPC classification number: G11C7/12 ,  G11C7/1075 ,  G11C11/419

Abstract: A pseudo dual port (PDP) memory is disclosed having a write driver that selectively precharges only one of a bit line and a complement bit line in a bit line pair responsive to a bit value to be written into an accessed bitcell while discharging a remaining one of the bit line and the complement bit line. In this fashion, the cleanup time between a read operation and a write operation during a read/write clock cycle is advantageously reduced.

Abstract translation: 公开了一种伪双端口（PDP）存储器，其具有写入驱动器，该写入驱动器响应于要写入访问的位单元的位值而选择性地仅对位线对中的一个位线进行充电，同时放电剩余的一个 的位线和补码位线。 以这种方式，有利地减少了在读/写时钟周期期间读操作和写操作之间的清理时间。

公开(公告)号：US08958226B2

公开(公告)日：2015-02-17

申请号：US13730524

申请日：2012-12-28

Applicant: Qualcomm Incorporated

Inventor： Esin Terzioglu ,  Nishith Desai ,  Rakesh Vattikonda ,  ChangHo Jung ,  Sei Seung Yoon

IPC: G11C15/04 ,  G11C15/00

CPC classification number: G11C15/04 ,  G11C15/00 ,  G11C15/043 ,  G11C15/046

Abstract: A static, ternary content addressable memory (TCAM) includes a key cell and a mask cell coupled to intermediate match lines. The key cell is coupled to a first pull-down transistor and a first pull-up transistor. The mask cell is coupled to a second pull-down transistor and a second pull-up transistor. The first pull-down transistor and second pull-down transistor are connected in parallel and the first pull-up transistor and second pull-up transistor are connected in series. A match line output is also coupled to the first pull-down transistor and second pull-down transistor and further coupled to the first pull-up transistor and second pull-up transistor.

Abstract translation: 静态三元内容可寻址存储器（TCAM）包括密钥单元和耦合到中间匹配行的掩码单元。 关键单元耦合到第一下拉晶体管和第一上拉晶体管。 掩模单元耦合到第二下拉晶体管和第二上拉晶体管。 第一下拉晶体管和第二下拉晶体管并联连接，第一上拉晶体管和第二上拉晶体管串联连接。 匹配线输出还耦合到第一下拉晶体管和第二下拉晶体管，并且还耦合到第一上拉晶体管和第二上拉晶体管。