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公开(公告)号：US10069474B2
公开(公告)日：2018-09-04
申请号：US15137662
申请日：2016-04-25
发明人： Changhan Hobie Yun , Chengjie Zuo , Daeik Daniel Kim , Mario Francisco Velez , Niranjan Sunil Mudakatte , Je-Hsiung Jeffrey Lan , David Francis Berdy , Yunfei Ma , Robert Paul Mikulka , Jonghae Kim
IPC分类号： H03H9/05 , H03H9/10 , H03H9/15 , H03H3/02 , H01F17/02 , H05K1/18 , H03H9/54 , H05K3/46 , H05K1/03 , H05K3/00 , H03H3/08 , H03H9/64 , H01F17/00 , H03H7/01 , H03H7/46
摘要： A device includes an acoustic resonator embedded within an encapsulating structure that at least partially encapsulates the acoustic resonator. The device includes an inductor electrically connected to the acoustic resonator. At least a portion of the inductor is embedded in the encapsulating structure.
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12.发明授权Face-up substrate integration with solder ball connection in semiconductor package 有权半导体封装中与焊球连接的正面衬底集成公开(公告)号：US09468098B2
公开(公告)日：2016-10-11
申请号：US14220913
申请日：2014-03-20
发明人： Daeik Daniel Kim , Jonghae Kim , Chengjie Zuo , Changhan Hobie Yun , Mario Francisco Velez , Robert Paul Mikulka
IPC分类号： H01L23/538 , H05K1/11 , H05K1/03 , H05K1/18 , H05K3/30 , H05K3/40 , H01L23/48 , H01L23/64 , H05K1/02 , H05K3/36 , H05K1/14 , H05K1/16 , H05K3/34
CPC分类号： H05K3/303 , H01L23/48 , H01L23/5385 , H01L23/645 , H01L2924/0002 , H01L2924/19101 , H05K1/0243 , H05K1/0306 , H05K1/111 , H05K1/141 , H05K1/144 , H05K1/165 , H05K1/18 , H05K3/3436 , H05K3/368 , H05K3/4007 , H05K3/4015 , H05K2201/1003 , H05K2201/10477 , H05K2201/10719 , H05K2201/10734 , H05K2201/10977 , H05K2203/041 , H05K2203/1316 , Y10T29/4902 , Y10T29/49126 , Y10T29/4913 , Y10T29/49146 , H01L2924/00
摘要： Systems and methods relate to a semiconductor package comprising a first substrate or a 2D passive-on-glass (POG) structure with a passive component and a first set of one or more package pads formed on a face of a glass substrate. The semiconductor package also includes a second or laminate substrate with a second set of one or more package pads formed on a face of the second or laminate substrate. Solder balls are dropped, configured to contact the first set of one or more package pads with the second set of one or more package pads, wherein the first substrate or the 2D POG structure is placed face-up on the face of the second or laminate substrate. A printed circuit board (PCB) can be coupled to a bottom side of the second or laminate substrate.
摘要翻译： 系统和方法涉及包括第一衬底或2D无源玻璃（POG）结构的半导体封装，其具有无源部件和形成在玻璃衬底的表面上的一个或多个封装焊盘的第一组。 半导体封装还包括具有第二组一个或多个封装焊盘的第二或层压衬底，其形成在第二层压衬底的表面上。 焊球被落下，被配置为使第一组一个或多个封装焊盘与第二组一个或多个封装焊盘接触，其中第一基板或2D POG结构朝上放置在第二或层压板的表面上 基质。 印刷电路板（PCB）可以耦合到第二或层压基板的底侧。
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13.发明授权Thick conductive stack plating process with fine critical dimension feature size for compact passive on glass technology 有权厚导电叠层电镀工艺，具有精细的临界尺寸特征尺寸，适用于紧凑的被动玻璃技术公开(公告)号：US09343399B2
公开(公告)日：2016-05-17
申请号：US14149530
申请日：2014-01-07
发明人： Je-Hsiung Lan , Chengjie Zuo , Changhan Hobie Yun , Jonghae Kim , Daeik Daniel Kim , Mario Francisco Velez , Robert Paul Mikulka , Niranjan Sunil Mudakatte
IPC分类号： H01L21/02 , H01L23/498 , H01L23/522 , H01L23/64 , H01L27/01 , H01L27/08 , H01L49/02
CPC分类号： H01L23/49822 , H01L23/5222 , H01L23/5227 , H01L23/642 , H01L23/645 , H01L27/016 , H01L27/0805 , H01L28/10 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit device includes a substrate, and a first interlayer dielectric layer on the substrate that includes a first conductive layer and a second conductive layer. The integrated circuit device also includes a first conductive stack including a third conductive layer coupled to a portion of the second conductive layer with a first via. The integrated circuit device further includes a second conductive stack comprising a fourth conductive layer directly on a portion of the third conductive layer that is isolated from the substrate. The integrated circuit device also includes a second interlayer dielectric layer surrounding the third conductive layer and the fourth conductive layer.
摘要翻译： 集成电路器件包括衬底，以及在衬底上的包括第一导电层和第二导电层的第一层间电介质层。 集成电路器件还包括第一导电叠层，其包括用第一通孔耦合到第二导电层的一部分的第三导电层。 集成电路器件还包括第二导电叠层，其包括直接位于与衬底隔离的第三导电层的一部分上的第四导电层。 集成电路器件还包括围绕第三导电层和第四导电层的第二层间介质层。
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公开(公告)号：US10354795B2
公开(公告)日：2019-07-16
申请号：US15242007
申请日：2016-08-19
发明人： Daeik Daniel Kim , Chengjie Zuo , Changhan Hobie Yun , Mario Francisco Velez , Robert Paul Mikulka , Xiangdong Zhang , Jonghae Kim , Je-Hsiung Lan
摘要： A method includes forming a first conductive spiral and a second conductive spiral of a spiral inductor coupled to a substrate. The second conductive spiral overlays the first conductive spiral. A first portion of an innermost turn of the spiral inductor has a first thickness in a direction perpendicular to the substrate. The first portion of the innermost turn includes a first portion of the first conductive spiral and does not include the second conductive spiral. A second portion of the innermost turn includes a first portion of the second conductive spiral. A portion of an outermost turn of the spiral inductor has a second thickness in the direction perpendicular to the substrate. The second thickness is greater than the first thickness. The portion of the outermost turn includes a second portion of the first conductive spiral and a second portion of the second conductive spiral.
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公开(公告)号：US10290414B2
公开(公告)日：2019-05-14
申请号：US14841132
申请日：2015-08-31
发明人： Changhan Hobie Yun , Mario Francisco Velez , Chengjie Zuo , Daeik Daniel Kim , David Francis Berdy , Je-Hsiung Jeffrey Lan , Jonghae Kim , Niranjan Sunil Mudakatte , Robert Paul Mikulka
IPC分类号： H01F5/00 , H01F27/28 , H01F27/245 , H01F41/14 , H01F41/04 , H01F17/00 , H01F41/32 , H01L23/64 , H05K1/16
摘要： A substrate includes a first dielectric layer, a magnetic core at least partially in the first dielectric layer, where the magnetic core comprises a first non-horizontal thin film magnetic (TFM) layer. The substrate also includes a first inductor that includes a plurality of first interconnects, where the first inductor is positioned in the substrate to at least partially surround the magnetic core. The magnetic core may further include a second non-horizontal thin film magnetic (TFM) layer. The magnetic core may further include a core layer. The magnetic core may further include a third thin film magnetic (TFM) layer, and a fourth thin film magnetic (TFM) layer that is substantially parallel to the third thin film magnetic (TFM) layer.
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公开(公告)号：US09876513B2
公开(公告)日：2018-01-23
申请号：US15088019
申请日：2016-03-31
发明人： Changhan Hobie Yun , David Francis Berdy , Chengjie Zuo , Daeik Daniel Kim , Mario Francisco Velez , Niranjan Sunil Mudakatte , Robert Paul Mikulka
CPC分类号： H04B1/0057 , H01L2224/11 , H03H3/00 , H03H7/0115 , H03H7/463 , H03H2001/0085
摘要： A three dimensional (3D) multiplexer structure may include a first two dimensional (2D) inductor capacitor (LC) filter layer. The first 2D LC filter layer may include a first 2D spiral inductor and a first capacitor(s). The 3D multiplexer structure may also include a second 2D LC filter layer. The second 2D LC filter layer may include a second 2D spiral inductor and a second capacitor(s) stacked directly on and communicably coupled to the first 2D LC filter.
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公开(公告)号：US09666362B2
公开(公告)日：2017-05-30
申请号：US15046302
申请日：2016-02-17
发明人： David Francis Berdy , Chengjie Zuo , Daeik Daniel Kim , Changhan Hobie Yun , Mario Francisco Velez , Robert Paul Mikulka , Jonghae Kim
CPC分类号： H01F41/041 , H01F17/0013 , H01F27/2804 , H01F27/29 , H01F2017/004 , H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： A three-dimensional (3D) orthogonal inductor pair is embedded in and supported by a substrate, and has a first inductor having a first coil that winds around a first winding axis and a second inductor having a second coil that winds around a second winding axis. The second winding axis is orthogonal to the first winding axis. The second winding axis intersects the first winding axis at an intersection point that is within the substrate.
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18.发明授权公开(公告)号：US09425761B2
公开(公告)日：2016-08-23
申请号：US14055707
申请日：2013-10-16
发明人： Chengjie Zuo , Jonghae Kim , Changhan Hobie Yun , Daeik Daniel Kim , Mario Francisco Velez , Je-Hsiung Lan , Robert Paul Mikulka , Matthew Michael Nowak
CPC分类号： H03H7/0138 , H03H7/0115 , Y10T29/417
摘要： A filter includes a glass substrate having through substrate vias. The filter also includes capacitors supported by the glass substrate. The capacitors may have a width and/or thickness less than a printing resolution. The filter also includes a 3D inductor within the substrate. The 3D inductor includes a first set of traces on a first surface of the glass substrate coupled to the through substrate vias. The 3D inductor also includes a second set of traces on a second surface of the glass substrate coupled to opposite ends of the through substrate vias. The second surface of the glass substrate is opposite the first surface of the glass substrate. The through substrate vias and traces operate as the 3D inductor. The first set of traces and the second set of traces may also have a width and/or thickness less than the printing resolution.
摘要翻译： 滤光器包括具有通过基板通孔的玻璃基板。 滤波器还包括由玻璃基板支撑的电容器。 电容器可以具有小于打印分辨率的宽度和/或厚度。 滤波器还包括衬底内的3D电感器。 3D电感器包括耦合到贯穿衬底通孔的玻璃衬底的第一表面上的第一组迹线。 3D电感器还包括耦合到贯通衬底通孔的相对端的玻璃衬底的第二表面上的第二组迹线。 玻璃基板的第二表面与玻璃基板的第一表面相对。 贯通衬底通孔和迹线作为3D电感器工作。 第一组迹线和第二组迹线也可以具有小于打印分辨率的宽度和/或厚度。
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19.发明授权Systems for reducing magnetic coupling in integrated circuits (ICS), and related components and methods 有权用于减少集成电路（ICS）中磁耦合的系统，以及相关组件和方法公开(公告)号：US09264013B2
公开(公告)日：2016-02-16
申请号：US14019821
申请日：2013-09-06
发明人： Chengjie Zuo , Jonghae Kim , Daeik Daniel Kim , Mario Francisco Velez , Changhan Hobie Yun , Je-Hsiung Jeffrey Lan , Robert Paul Mikulka , Matthew Michael Nowak
CPC分类号： H03H7/463 , H03H3/00 , Y10T29/4902
摘要： Systems for reducing magnetic coupling in integrated circuits (ICs) are disclosed. Related components and methods are also disclosed. The ICs have a plurality of inductors. Each inductor generates a magnetic flux that has a discernible axis. To reduce magnetic coupling between the inductors, the flux axes are designed so as to be non-parallel. In particular, by making the flux axes of the inductors non-parallel to one another, magnetic coupling between the inductors is reduced relative to the situation where the flux axes are parallel. This arrangement may be particularly well suited for use in diplexers having a low pass and a high pass filter.
摘要翻译： 公开了用于减小集成电路（IC）中的磁耦合的系统。 还公开了相关的部件和方法。 IC具有多个电感器。 每个电感器产生具有可辨别轴线的磁通量。 为了减小电感器之间的磁耦合，磁通轴被设计成不平行。 特别地，通过使电感器的磁通轴彼此不平行，相对于磁通轴平行的情况，电感器之间的磁耦合减小。 这种布置可以特别适用于具有低通和高通滤波器的双工器。
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公开(公告)号：US10103703B2
公开(公告)日：2018-10-16
申请号：US15161138
申请日：2016-05-20
发明人： Changhan Hobie Yun , David Francis Berdy , Chengjie Zuo , Daeik Daniel Kim , Jonghae Kim , Mario Francisco Velez , Niranjan Sunil Mudakatte , Robert Paul Mikulka
IPC分类号： H03H7/01 , H01F5/00 , H01F41/04 , H01P1/203 , H03H7/09 , H05K1/18 , H03H1/00 , H05K1/02 , H05K1/03 , H05K1/11 , H05K1/16 , H05K3/00 , H05K3/18 , H05K3/40 , H01P1/213 , H01P5/12 , H03H7/46
摘要： The present disclosure provides circuits and methods for fabricating circuits. A circuit may include an insulator having a first surface, a second surface, a periphery, a first subset of circuit elements disposed on the first surface, a second subset of circuit elements disposed on the second surface, and at least one conductive sidewall disposed on the periphery, wherein the conductive sidewall electrically couples the first subset of circuit elements to the second subset of circuit elements.
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