中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

21 records (took 0.013 seconds)

    SOC DESIGN WITH CRITICAL TECHNOLOGY PITCH ALIGNMENT
    11.
    发明申请
    SOC DESIGN WITH CRITICAL TECHNOLOGY PITCH ALIGNMENT 有权
    SOC设计与关键技术垂直对齐

    公开(公告)号：US20150028495A1

    公开(公告)日：2015-01-29

    申请号：US14338229

    申请日：2014-07-22

    Applicant: QUALCOMM Incorporated

    Inventor： Xiangdong CHEN ,  Ohsang KWON ,  Esin TERZIOGLU ,  Hadi BUNNALIM

    IPC: H01L23/528 ,  H01L23/522

    CPC classification number: H01L23/5226 ,  H01L23/498 ,  H01L23/528 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An SOC apparatus includes a plurality of gate interconnects with a minimum pitch g, a plurality of metal interconnects with a minimum pitch m, and a plurality of vias interconnecting the gate interconnects and the metal interconnects. The vias have a minimum pitch v. The values m, g, and v are such that g2+m2≧V2 and an LCM of g and m is less than 20 g. The SOC apparatus may further include a second plurality of metal interconnects with a minimum pitch of m2, where m2>m and the LCM of g, m, and m2 is less than 20 g.

    Abstract translation: SOC装置包括具有最小间距g的多个栅极互连，具有最小间距m的多个金属互连以及互连栅极互连和金属互连的多个通孔。 通孔具有最小间距v。值m，g和v使得g2 +m2≥V2，g和m的LCM小于20g。 SOC装置还可以包括具有最小间距m2的第二多个金属互连，其中m2> m且g，m和m2的LCM小于20g。

    STANDARD CELL ARCHITECTURE FOR GATE TIE-OFF
    12.
    发明申请
    STANDARD CELL ARCHITECTURE FOR GATE TIE-OFF 审中-公开

    公开(公告)号：US20200176563A1

    公开(公告)日：2020-06-04

    申请号：US16781856

    申请日：2020-02-04

    Applicant: QUALCOMM Incorporated

    Inventor： Xiangdong CHEN ,  Venugopal BOYNAPALLI ,  Hyeokjin LIM

    IPC: H01L29/06 ,  H01L27/02 ,  H01L27/118 ,  H01L23/528 ,  H01L29/66 ,  H01L23/522 ,  H01L23/532

    Abstract: A chip includes a first gate extended along a second lateral direction, a first source electrically coupled to a power rail, and a first metal interconnect extended along a first lateral direction approximately perpendicular to the second lateral direction, wherein the first metal interconnect lies above the first gate and the first source, and the first metal interconnect is configured to electrically couple the first gate to the first source. The chip also includes a second gate extended along the second lateral direction, a second source electrically coupled to the power rail, and a second metal interconnect extended along the first lateral direction, wherein the second metal interconnect lies above the second gate and second source, the second metal interconnect is configured to electrically couple the second gate to the second source, and the first metal interconnect is aligned with the second metal interconnect in the second lateral direction.

    LOW-AREA LOW CLOCK-POWER FLIP-FLOP
    14.
    发明申请
    LOW-AREA LOW CLOCK-POWER FLIP-FLOP 有权

    公开(公告)号：US20170257080A1

    公开(公告)日：2017-09-07

    申请号：US15061055

    申请日：2016-03-04

    Applicant: QUALCOMM Incorporated

    Inventor： Seid Hadi RASOULI ,  Xiangdong CHEN ,  Venugopal BOYNAPALLI

    IPC: H03K3/012 ,  H03K3/356

    CPC classification number: H03K3/012 ,  H03K3/356104 ,  H03K3/35625

    Abstract: In one example, the apparatus includes a first AND gate, a second AND gate, a first NOR gate, a second NOR gate, a third NOR gate, a first inverter, and a second inverter. The first AND gate output is coupled to the first NOR gate first input. The first NOR gate output is coupled to the second NOR gate first input. The second NOR gate output is coupled to the first NOR gate second input. The first inverter output is coupled to the first AND gate second input and the second NOR gate second input. The second AND gate first input is coupled to the first inverter output. The third NOR gate first input is coupled to the second NOR gate output. The third NOR gate second input is coupled to the second AND gate output. The second inverter output is coupled to the second AND gate second input.

    HYBRID COLORING METHODOLOGY FOR MULTI-PATTERN TECHNOLOGY
    15.
    发明申请
    HYBRID COLORING METHODOLOGY FOR MULTI-PATTERN TECHNOLOGY 审中-公开
    混合色彩方法多图案技术

    公开(公告)号：US20160370699A1

    公开(公告)日：2016-12-22

    申请号：US15182510

    申请日：2016-06-14

    Applicant: QUALCOMM Incorporated

    Inventor： Xiangdong CHEN ,  Hyeokjin Bruce LIM ,  Ohsang KWON ,  Mickael MALABRY ,  Jingwei ZHANG ,  Raymond George STEPHANY ,  Haining YANG ,  Kern RIM ,  Stanley Seungchul SONG ,  Mukul GUPTA ,  Foua VANG

    IPC: G03F1/70 ,  G06F17/50

    CPC classification number: G03F1/70 ,  G03F7/70433 ,  G03F7/70466 ,  G06F17/5068

    Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus for assigning feature colors for a multiple patterning process are provided. The apparatus receives integrated circuit layout information including a set of features and an assigned color of a plurality of colors for each feature of a first subset of features of the set of features. In addition, the apparatus performs color decomposition on a second subset of features to assign colors to features in the second subset of features. The second subset of features includes features in the set of features that are not included in the first subset of features with an assigned color.

    Abstract translation: 在本公开的一个方面，提供了一种方法，计算机可读介质和用于分配多个图案化处理的特征颜色的装置。 该装置接收集成电路布局信息，该信息包括一组特征的集合，以及针对特征集合的第一特征集的每个特征的多种颜色的分配颜色。 另外，该装置对特征的第二子集执行颜色分解，以将颜色分配给第二特征子集中的特征。 特征的第二子集包括不包括在具有分配颜色的特征的第一子集中的特征集合中的特征。

    CONDUCTIVE LAYER ROUTING
    18.
    发明申请
    CONDUCTIVE LAYER ROUTING 有权
    导电层路由

    公开(公告)号：US20150194339A1

    公开(公告)日：2015-07-09

    申请号：US14283162

    申请日：2014-05-20

    Applicant: QUALCOMM Incorporated

    Inventor： Stanley Seungchul SONG ,  Kern RIM ,  Zhongze WANG ,  Jeffrey Junhao XU ,  Xiangdong CHEN ,  Choh Fei YEAP

    IPC: H01L21/768 ,  H01L23/48

    CPC classification number: H01L21/76802 ,  H01L21/76814 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/48 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods of fabricating middle of line (MOL) layers and devices including MOL layers. A method in accordance with an aspect of the present disclosure includes depositing a hard mask across active contacts to terminals of semiconductor devices of a semiconductor substrate. Such a method also includes patterning the hard mask to selectively expose some of the active contacts and selectively insulate some of the active contacts. The method also includes depositing a conductive material on the patterned hard mask and the exposed active contacts to couple the exposed active contacts to each other over an active area of the semiconductor devices.

    Abstract translation: 制造中间线（MOL）层和包括MOL层的器件的方法。 根据本公开的一个方面的方法包括将半导体衬底的半导体器件的端子上的活性触点沉积硬掩模。 这种方法还包括图案化硬掩模以选择性地暴露一些有源触点并选择性地绝缘一些有源触点。 该方法还包括在图案化的硬掩模和暴露的有源触点上沉积导电材料，以将暴露的有源触点彼此连接在半导体器件的有效区域上。

    SHUNT POWER RAIL WITH SHORT LINE EFFECT
    19.
    发明申请
    SHUNT POWER RAIL WITH SHORT LINE EFFECT 审中-公开

    公开(公告)号：US20200044440A1

    公开(公告)日：2020-02-06

    申请号：US16362417

    申请日：2019-03-22

    Applicant: QUALCOMM Incorporated

    Inventor： John Jianhong ZHU ,  Xiangdong CHEN ,  Haining YANG ,  Kern RIM

    IPC: H02H9/04 ,  H01Q1/22 ,  H02J7/00

    Abstract: A cell circuit includes a first power rail, having a first line length, in a first layer. The first power rail is configured to receive a first voltage for the cell circuit. The cell circuit includes multiple lines in a second layer and a shunt in a third layer. The shunt is electrically coupled to the first power rail and a first set of lines of the multiple lines. The shunt has a second line length shorter than the first line length. The cell circuit includes another shunt in t the third layer. The other shunt is also parallel to the first power rail. The other shunt is electrically coupled to the first power rail and a second set of lines of the multiple lines. The other shunt has a third line length shorter than the first line length.

Patent Agency Ranking