公开(公告)号：US20080111184A1

公开(公告)日：2008-05-15

申请号：US11559460

申请日：2006-11-14

申请人： Jochen Beintner ,  Gary B. Bronner ,  Ramachandra Divakaruni ,  Yujun Li

发明人： Jochen Beintner ,  Gary B. Bronner ,  Ramachandra Divakaruni ,  Yujun Li

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7851 ,  H01L29/66795

摘要： A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate.

摘要翻译： 提供了在半导体衬底上制造多个FinFET的方法，其中仅使用单个蚀刻工艺限定每个单个FinFET的栅极宽度，而不是两个或更多个。 本发明的方法导致改善的栅极宽度控制和在基板的整个表面上每个单独栅极的栅极宽度的变化较小。 本发明的方法通过利用改进的侧壁图像转印（SIT）工艺实现上述，其中采用稍后被栅极导体替代的绝缘间隔物，并且使用高密度底部向上氧化物填充物将栅极与衬底隔离 。

公开(公告)号：US06905976B2

公开(公告)日：2005-06-14

申请号：US10249771

申请日：2003-05-06

申请人： Jochen Beintner ,  Yujun Li ,  Naim Moumen ,  Porshia Shane Wrschka

发明人： Jochen Beintner ,  Yujun Li ,  Naim Moumen ,  Porshia Shane Wrschka

IPC分类号： H01L29/423 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L21/302

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L21/28044 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/49 ,  H01L29/665 ,  Y10S438/933

摘要： The structure and method of forming a notched gate MOSFET disclosed herein addresses such problems as device reliability. A gate dielectric (e.g. gate oxide) is formed on the surface of an active area on the semiconductor substrate, preferably defined by an isolation trench region. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium) (SiGe). The sidewalls of the polysilicon layer are then laterally etched, selective to the SiGe layer to create a notched gate conductor structure, with the SiGe layer being broader than the underlying polysilicon layer. Sidewall spacers are preferably formed on sidewalls of the SiGe layer and the polysilicon layer. A silicide layer is preferably formed as a self-aligned silicide from a polysilicon layer deposited over the SiGe layer, to reduce resistance of the gate conductor. One or more other processing steps (e.g. source and drain implants, extension implants, and pocket lightly doped drain (LDD) implants), gate conductor stack doping, and silicidation are preferably performed in completing the transistor.

摘要翻译： 本文公开的形成缺口栅极MOSFET的结构和方法解决了诸如器件可靠性的问题。 栅电介质（例如栅极氧化物）形成在半导体衬底上的有源区的表面上，优选由隔离沟槽区限定。 然后在栅极电介质上沉积多晶硅层。 该步骤之后是沉积一层硅锗）（SiGe）。 然后横向蚀刻多晶硅层的侧壁，对SiGe层有选择性，以产生刻蚀的栅极导体结构，其中SiGe层比下面的多晶硅层宽。 侧壁间隔物优选形成在SiGe层和多晶硅层的侧壁上。 硅化物层优选从沉积在SiGe层上的多晶硅层形成为自对准硅化物，以降低栅极导体的电阻。 优选在完成晶体管时执行一个或多个其它处理步骤（例如源极和漏极注入，延伸注入和袖带轻掺杂漏极（LDD）注入），栅极导体堆叠掺杂和硅化。

公开(公告)号：US06329704B1

公开(公告)日：2001-12-11

申请号：US09458530

申请日：1999-12-09

申请人： Hiroyuki Akatsu ,  Omer H. Dokumaci ,  Suryanarayan G. Hegde ,  Yujun Li ,  Rajesh Rengarajan ,  Paul A. Ronsheim

发明人： Hiroyuki Akatsu ,  Omer H. Dokumaci ,  Suryanarayan G. Hegde ,  Yujun Li ,  Rajesh Rengarajan ,  Paul A. Ronsheim

IPC分类号： H01L29167

CPC分类号： H01L21/2652 ,  H01L21/2254 ,  H01L21/2255 ,  H01L29/6659

摘要： A process for forming an ultra-shallow junction depth, doped region within a silicon substrate. The process includes forming a dielectric film on the substrate, then implanting an ionic dopant species into the structure. The profile of the implanted species includes a population implanted through the dielectric film and into the silicon substrate, and a peak concentration deliberately confined in the dielectric film in close proximity to the interface between the dielectric film and the silicon substrate. A high-energy, low-dosage implant process is used and produces a structure that is substantially free of dislocation loops and other defect clusters. An annealing process is used to drive the peak concentration closer to the interface, and some of the population of the originally implanted species from the dielectric film into the silicon substrate. A low thermal budget is maintained because of the proximity of the as-implanted peak concentration to the interface and the presence of species implanted through the dielectric film and into the substrate.

摘要翻译： 一种用于在硅衬底内形成超浅结深度掺杂区的工艺。 该方法包括在衬底上形成电介质膜，然后将离子掺杂剂物质注入结构中。 植入物种的轮廓包括通过电介质膜注入硅衬底中的群体，以及刻意限制在电介质膜中的接近于介电膜和硅衬底之间界面的峰值浓度。 使用高能量，低剂量的植入工艺，并且产生基本上不含位错环和其它缺陷簇的结构。 使用退火工艺来驱动更接近界面的峰值浓度，以及从电介质膜到硅衬底的最初注入物质的一些群体。 由于植入的峰浓度与界面的接近以及通过电介质膜注入并进入衬底的物质的存在，维持了低热量预算。

公开(公告)号：US06297530B1

公开(公告)日：2001-10-02

申请号：US09418181

申请日：1998-12-28

申请人： Hiroyuki Akatsu ,  Yujun Li ,  Jochen Beintner

发明人： Hiroyuki Akatsu ,  Yujun Li ,  Jochen Beintner

IPC分类号： H01L2976

CPC分类号： H01L29/66583 ,  H01L21/823412 ,  H01L29/105

摘要： A short channel insulated gate field effect transistor has within the semiconductor body that houses the transistor a buried layer of the same conductivity type as the body but of higher impurity concentration. The buried layer is below the channel region and essentially extends only the distance between the drain and source regions of the transistor. The process to form the device provides high concentration in the region under the gate to suppress lateral depletion region expansion, while keeping a gradual junction in the vertical direction.

摘要翻译： 短沟道绝缘栅场效应晶体管在半导体本体内部具有与晶体管相同的导电类型的掩埋层，但具有较高的杂质浓度。 掩埋层在沟道区下方，并且基本上只延伸晶体管的漏极和源极区之间的距离。 形成器件的过程在栅极下方的区域提供高浓度，以抑制横向耗尽区域膨胀，同时保持垂直方向上的逐渐连接。

公开(公告)号：US08614485B2

公开(公告)日：2013-12-24

申请号：US12342655

申请日：2008-12-23

申请人： Jochen Beintner ,  Gary B. Bronner ,  Ramachandra Divakaruni ,  Yujun Li

发明人： Jochen Beintner ,  Gary B. Bronner ,  Ramachandra Divakaruni ,  Yujun Li

IPC分类号： H01L29/78

CPC分类号： H01L29/7851 ,  H01L29/66795

摘要： A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate.

摘要翻译： 提供了在半导体衬底上制造多个FinFET的方法，其中仅使用单个蚀刻工艺限定每个单个FinFET的栅极宽度，而不是两个或更多个。 本发明的方法导致改善的栅极宽度控制和在基板的整个表面上每个单独栅极的栅极宽度的变化较小。 本发明的方法通过利用改进的侧壁图像转印（SIT）工艺实现上述，其中采用稍后被栅极导体替代的绝缘间隔物，并且使用高密度底部向上氧化物填充物将栅极与衬底隔离 。

公开(公告)号：US20080246059A1

公开(公告)日：2008-10-09

申请号：US12141878

申请日：2008-06-18

申请人： Yujun Li ,  Kenneth T. Settlemyer ,  Jochen Beintner

发明人： Yujun Li ,  Kenneth T. Settlemyer ,  Jochen Beintner

IPC分类号： H01L29/772 ,  H01L21/306

CPC分类号： H01L21/84 ,  H01L21/30608 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/66772 ,  H01L29/66818 ,  H01L29/785

摘要： A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substantially parallel with selected crystallographic planes of the pedestal and of a supporting member. The pedestal is wet etched with an anisotropic solution containing ammonium hydroxide. The sidewalls of the pedestal become faceted forming a segment in the pedestal with a reduced cross section. The dopant concentration in the reduced cross section segment is chosen to be sufficiently high for it to provide for electrical continuity through the pedestal.

摘要翻译： 提出了一种制造方法和场效应器件结构，其减少源/漏电容并允许器件接触。 制造基于Si的材料基座，其顶表面和其侧壁的取向方向基本上平行于基座和支撑构件的选定结晶平面。 用包含氢氧化铵的各向异性溶液湿式蚀刻基座。 基座的侧壁变小，在基座上形成截面减小的部分。 选择减小的横截面段中的掺杂剂浓度足够高以使其提供穿过基座的电连续性。

公开(公告)号：US20070298004A1

公开(公告)日：2007-12-27

申请号：US11820550

申请日：2007-06-20

申请人： Yujun Li

发明人： Yujun Li

IPC分类号： A61K8/40 ,  A61Q5/12

CPC分类号： A61K8/416 ,  A61K8/342 ,  A61K8/42 ,  A61K8/891 ,  A61K8/898 ,  A61Q5/12

摘要： Disclosed is a conditioning composition comprising: an asymmetric di-alkyl ammonium salt cationic surfactant; a high melting point fatty compound; and an aqueous carrier. The composition of the present invention can provide improved ease-to-rinse feel while maintaining conditioning benefits.

摘要翻译： 公开了一种调理组合物，其包含：不对称二烷基铵盐阳离子表面活性剂; 高熔点脂肪化合物; 和水性载体。 本发明的组合物可以提供改善的易于冲洗的感觉，同时保持调理的好处。

公开(公告)号：US07294879B2

公开(公告)日：2007-11-13

申请号：US10622477

申请日：2003-07-18

申请人： Xiangdong Chen ,  Geng Wang ,  Yujun Li ,  Qiqing C. Ouyang

发明人： Xiangdong Chen ,  Geng Wang ,  Yujun Li ,  Qiqing C. Ouyang

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L29/66181 ,  H01L27/10864

摘要： A vertical pass transistor used in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical pass transistor for the DRAM cell incorporates two gate materials having different work functions. The gate material near the storage node is n-type doped polysilicon. The gate material near the bit line diffusion is made of silicide or metal having a higher work function than the n-polysilicon. The novel device structure shows several advantages: the channel doping is reduced while maintaining a high Vt and a low sub-threshold leakage current; the carrier mobility improves with the reduced channel doping; the body effect of the device is reduced which improves the write back current; and the sub-threshold swing is reduced because of the low channel doping.

摘要翻译： 在DRAM单元中使用的用于保持低总漏电流并提供足够的驱动电流的垂直传输晶体管与制造这种器件的方法一起被描述。 晶体管栅极被设计代替通道。 用于DRAM单元的垂直传输晶体管包括具有不同功函数的两个栅极材料。 存储节点附近的栅极材料为n型掺杂多晶硅。 位线扩散附近的栅极材料由具有比n-多晶硅更高的功函数的硅化物或金属制成。 该新颖的器件结构显示出几个优点：沟道掺杂减少，同时保持高Vt和低的亚阈值漏电流; 载流子迁移率随着沟道掺杂的减少而提高; 减少了器件的体效，提高了回写电流; 并且由于低通道掺杂，子阈值摆幅减小。

公开(公告)号：US07018551B2

公开(公告)日：2006-03-28

申请号：US10730234

申请日：2003-12-09

申请人： Jochen C. Beintner ,  Dureseti Chidambarrao ,  Yujun Li ,  Kenneth T. Settlemyer, Jr.

发明人： Jochen C. Beintner ,  Dureseti Chidambarrao ,  Yujun Li ,  Kenneth T. Settlemyer, Jr.

IPC分类号： B44C1/22

CPC分类号： H01L29/785 ,  H01L21/3086 ,  H01L21/3088 ,  H01L29/66795

摘要： A method of forming integrated circuits having FinFET transistors includes a method of forming sub-lithographic fins, in which a mask defining a block of silicon including a pair of fins in reduced in width or pulled back by the thickness of one fin on each side, after which a second mask is formed around the first mask, so that after the first mask is removed, an aperture remains in the second mask having the width of the separation distance between the pair of fins. When the silicon is etched through the aperture, the fins are protected by the second mask, thereby defining fin thickness by the pullback step. An alternative method uses lithography of opposite polarity, first defining the central etch aperture between the two fins lithographically, then expanding the width of the aperture by a pullback step, so that filling the widened aperture with an etch-resistant plug defines the outer edges of the pair of fins, thereby setting the fin width without an alignment kstep.

摘要翻译： 一种形成具有FinFET晶体管的集成电路的方法包括形成次光刻鳍片的方法，其中限定包含一对鳍片的硅块的掩模，所述掩模的宽度被减小或者被拉回每边的一个鳍片的厚度， 之后在第一掩模周围形成第二掩模，使得在去除第一掩模之后，在第二掩模中保留具有一对散热片之间的间隔距离的宽度的孔。 当通过孔蚀刻硅时，翅片被第二掩模保护，从而通过拉回步骤限定翅片厚度。 一种替代方法是使用相反极性的光刻法，首先在两个散热片之间光刻地限定中心蚀刻孔径，然后通过拉回步骤扩大孔径的宽度，以便用耐蚀刻塞子填充加宽的孔径限定了 一对翅片，从而设置翅片宽度而没有对准kstep。

公开(公告)号：US06930004B2

公开(公告)日：2005-08-16

申请号：US10604731

申请日：2003-08-13

申请人： Geng Wang ,  Kevin Mcstay ,  Mary Elizabeth Weybright ,  Yujun Li ,  Dureseti Chidambarrao

发明人： Geng Wang ,  Kevin Mcstay ,  Mary Elizabeth Weybright ,  Yujun Li ,  Dureseti Chidambarrao

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8242

CPC分类号： H01L27/10876 ,  H01L21/26586 ,  H01L27/10864 ,  H01L29/1041 ,  H01L29/66537 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/945

摘要： A method of formation of a deep trench vertical transistor is provided. A deep trench with a sidewall in a doped semiconductor substrate is formed. The semiconductor substrate includes a counterdoped drain region in the surface thereof and a channel alongside the sidewall. The drain region has a top level and a bottom level. A counterdoped source region is formed in the substrate juxtaposed with the sidewall below the channel. A gate oxide layer is formed on the sidewalls of the trench juxtaposed with a gate conductor. Perform the step of recessing the gate conductor below the bottom level of the drain region followed by performing angled ion implantation at an angle θ+δ with respect to vertical of a counterdopant into the channel below the source region and performing angled ion implantation at an angle θ with respect to vertical of a dopant into the channel below the source.

摘要翻译： 提供了形成深沟槽垂直晶体管的方法。 在掺杂半导体衬底中形成具有侧壁的深沟槽。 半导体衬底在其表面中包括反向漏极区域和沿着侧壁的通道。 漏极区域具有顶层和底层。 反向掺杂的源极区域形成在与通道下方的侧壁并置的衬底中。 栅极氧化层形成在与栅极导体并置的沟槽的侧壁上。 执行将栅极导体凹入低于漏极区域的底部电平的步骤，然后相对于反向掺杂物的垂直角进行成角度的离子注入进入源极区域下方的沟道，并以一定角度进行成角度的离子注入 θ相对于掺杂剂的垂直方向到源下方的通道。