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    BOUNDARY SCAN CHAIN FOR STACKED MEMORY
    11.
    发明申请
    BOUNDARY SCAN CHAIN FOR STACKED MEMORY 有权
    用于堆叠存储器的边界扫描链

    公开(公告)号：US20130173971A1

    公开(公告)日：2013-07-04

    申请号：US13340470

    申请日：2011-12-29

    申请人： David J. Zimmerman

    发明人： David J. Zimmerman

    IPC分类号： G11C29/10 ,  G06F11/25 ,  G06F11/263 ,  G01R31/3177

    CPC分类号： G11C29/32 ,  G01R31/3177 ,  G01R31/318513 ,  G01R31/318558 ,  G01R31/318572 ,  G11C5/04 ,  G11C11/4087 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A boundary scan chain for stacked memory. An embodiment of a memory device includes a system element and a memory stack including one or more memory die layers, each memory die layer including input-output (I/O) cells and a boundary scan chain for the I/O cells. A boundary scan chain of a memory die layer includes a scan chain portion for each of the I/O cells, the scan chain portion for an I/O cell including a first scan logic multiplexer a scan logic latch, an input of the scan logic latch being coupled with an output of the first scan logic multiplexer, and a decoder to provide command signals to the boundary scan chain.

    摘要翻译： 堆叠式存储器的边界扫描链。 存储器件的实施例包括系统元件和包括一个或多个存储管芯层的存储器堆叠，每个存储器管芯层包括用于I / O单元的输入输出（I / O）单元和边界扫描链。 存储芯片层的边界扫描链包括用于每个I / O单元的扫描链部分，用于I / O单元的扫描链部分包括第一扫描逻辑多路复用器，扫描逻辑锁存器，扫描逻辑的输入 锁存器与第一扫描逻辑多路复用器的输出耦合，以及解码器，用于向边界扫描链提供命令信号。

    INTERFACE FOR STORAGE DEVICE ACCESS OVER MEMORY BUS
    13.
    发明申请
    INTERFACE FOR STORAGE DEVICE ACCESS OVER MEMORY BUS 有权
    用于存储器存储器的接口通过存储器总线访问

    公开(公告)号：US20150269100A1

    公开(公告)日：2015-09-24

    申请号：US14731183

    申请日：2015-06-04

    申请人： Shekoufeh Qawami ,  Rajesh Sundaram ,  David J. Zimmerman ,  Robert W. Faber

    发明人： Shekoufeh Qawami ,  Rajesh Sundaram ,  David J. Zimmerman ,  Robert W. Faber

    IPC分类号： G06F13/28 ,  G06F12/02 ,  G06F13/42 ,  G11C7/22 ,  G06F1/12 ,  G06F13/16

    CPC分类号： G06F13/28 ,  G06F1/12 ,  G06F12/0246 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/385 ,  G06F13/409 ,  G06F13/42 ,  G06F2212/7201 ,  G06F2212/7203 ,  G11C7/222 ,  H04L5/00 ,  H04L7/00 ,  Y02D10/14 ,  Y02D10/151

    摘要： A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.

    摘要翻译： 通过存储器总线访问非易失性存储器或存储器件。 存储器总线具有通常用于易失性存储器件的电接口。 耦合到总线的控制器向非易失性存储器件发送同步数据访问命令，并且基于来自非易失性存储器件的回复的期望定时从设备总线读取响应。 控制器基于何时发送命令和非易失性存储器件的特性来确定预期时序。 控制器可能不需要存储器总线上可用的所有电信号线，并且可以通过不同的电信号线组向不同组的非易失性存储器件发出数据访问命令。 存储器总线可以可用并且被配置用于与存储器控制器和易失性存储器设备或存储控制器和非易失性存储器设备一起使用。

    Input/output delay testing for devices utilizing on-chip delay generation
    14.
    发明授权
    Input/output delay testing for devices utilizing on-chip delay generation 有权
    使用片上延迟生成的器件的输入/输出延迟测试

    公开(公告)号：US09110134B2

    公开(公告)日：2015-08-18

    申请号：US13728741

    申请日：2012-12-27

    申请人： Tak M. Mak ,  Christopher J. Nelson ,  David J. Zimmerman ,  Derek B. Feltham

    发明人： Tak M. Mak ,  Christopher J. Nelson ,  David J. Zimmerman ,  Derek B. Feltham

    IPC分类号： G01R31/30 ,  G01R31/317

    CPC分类号： G01R31/31716 ,  G01R31/3016

    摘要： I/O delay testing for devices utilizing on-chip delay generation. An embodiment of an apparatus includes I/O buffer circuits, at least one of the buffer circuits including a transmitter and a receiver that are coupled for loop-back testing of the buffer circuit; and testing circuitry for the loop-back testing for the at least one buffer circuit, the loop-back testing including determining whether test data transmitted by the transmitter of the buffer circuit matches test data received by the respective coupled receiver. The testing circuitry includes a delay line to provide delay values from a transmit clock signal for the testing of the at least one buffer circuit, a counter to provide a count to choose one of the plurality of delay values, and test logic for the loop-back testing.

    摘要翻译： 利用片上延迟生成的器件进行I / O延迟测试。 装置的实施例包括I / O缓冲电路，缓冲电路中的至少一个包括被耦合用于缓冲电路的环回测试的发射机和接收机; 以及用于所述至少一个缓冲电路的环回测试的测试电路，所述环回测试包括确定由所述缓冲器电路的发射机发送的测试数据是否与由所述相应耦合的接收机接收的测试数据相匹配。 测试电路包括延迟线，用于从用于测试至少一个缓冲电路的发射时钟信号提供延迟值，提供计数以选择多个延迟值中的一个的计数器， 回测试。

    ON CHIP REDUNDANCY REPAIR FOR MEMORY DEVICES
    15.
    发明申请
    ON CHIP REDUNDANCY REPAIR FOR MEMORY DEVICES 有权
    用于存储器件的芯片冗余维修

    公开(公告)号：US20140013185A1

    公开(公告)日：2014-01-09

    申请号：US13976409

    申请日：2012-03-30

    申请人： Darshan Kobla ,  David J. Zimmerman ,  Vimal K. Natarajan

    发明人： Darshan Kobla ,  David J. Zimmerman ,  Vimal K. Natarajan

    IPC分类号： G06F11/10

    CPC分类号： G06F11/1016 ,  G11C11/4097 ,  G11C29/4401 ,  G11C2029/0407 ,  G11C2029/4402

    摘要： On chip redundancy repair for memory devices. An embodiment of a memory device includes a dynamic random-access memory (DRAM); and a system element coupled with the DRAM. The system element includes a memory controller for control of the DRAM, and repair logic coupled with the memory controller, the repair logic to hold addresses identified as failing addresses for defective areas of the DRAM. The repair logic is configured to receive a memory operation request and to implement redundancy repair for an operation address for the request.

    摘要翻译： 内存设备的片上冗余修复。 存储器件的实施例包括动态随机存取存储器（DRAM）; 以及与DRAM耦合的系统元件。 系统元件包括用于控制DRAM的存储器控​​制器，以及与存储器控制器耦合的修复逻辑，修复逻辑保存被识别为DRAM缺陷区域的故障地址的地址。 修复逻辑被配置为接收存储器操作请求并且为该请求的操作地址实施冗余修复。

    Interface for Storage Device Access Over Memory Bus
    17.
    发明申请
    Interface for Storage Device Access Over Memory Bus 有权
    通过内存总线访问存储设备的接口

    公开(公告)号：US20120297231A1

    公开(公告)日：2012-11-22

    申请号：US13111839

    申请日：2011-05-19

    申请人： Shekoufeh Qawami ,  Rajesh Sundaram ,  David J. Zimmerman ,  Robert W. Faber

    发明人： Shekoufeh Qawami ,  Rajesh Sundaram ,  David J. Zimmerman ,  Robert W. Faber

    IPC分类号： G06F1/12

    CPC分类号： G06F13/28 ,  G06F1/12 ,  G06F12/0246 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/385 ,  G06F13/409 ,  G06F13/42 ,  G06F2212/7201 ,  G06F2212/7203 ,  G11C7/222 ,  H04L5/00 ,  H04L7/00 ,  Y02D10/14 ,  Y02D10/151

    摘要： A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.

    摘要翻译： 通过存储器总线访问非易失性存储器或存储器件。 存储器总线具有通常用于易失性存储器件的电接口。 耦合到总线的控制器向非易失性存储器件发送同步数据访问命令，并且基于来自非易失性存储器件的回复的期望定时从设备总线读取响应。 控制器基于何时发送命令和非易失性存储器件的特性来确定预期时序。 控制器可能不需要存储器总线上可用的所有电信号线，并且可以通过不同的电信号线组向不同组的非易失性存储器件发出数据访问命令。 存储器总线可以可用并且被配置用于与存储器控制器和易失性存储器设备或存储控制器和非易失性存储器设备一起使用。

    Low speed access to dram
    18.
    发明申请
    Low speed access to dram 失效
    低速接入电话

    公开(公告)号：US20090316800A1

    公开(公告)日：2009-12-24

    申请号：US12583920

    申请日：2009-08-24

    申请人： David J. Zimmerman ,  Michael W. Williams

    发明人： David J. Zimmerman ,  Michael W. Williams

    IPC分类号： H04B3/00 ,  G06F12/06

    CPC分类号： G06F13/28 ,  G11C5/066 ,  G11C7/10 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/109 ,  G11C11/4076 ,  G11C11/4096

    摘要： Embodiments provide access to a memory over a high speed serial link at slower speeds than the high speed serial links regular operation. An embodiment may comprise a memory apparatus with a differential receiver coupled to a protocol recognition circuit, a low speed receiving circuit that has a first receiver coupled with a first input of the differential receiver and a second receiver coupled with a second input of the differential receiver, wherein the low speed receiving circuit is coupled with the protocol recognition circuit, allowing the first and second receivers to access the protocol recognition block at a different frequency than the differential receiver.

    摘要翻译： 实施例通过高速串行链路以比高速串行链路常规操作更慢的速度提供对存储器的访问。 实施例可以包括具有耦合到协议识别电路的差分接收器的存储器设备，具有与差分接收器的第一输入端耦合的第一接收器的低速接收电路和与差分接收器的第二输入端耦合的第二接收器 其中低速接收电路与协议识别电路耦合，允许第一和第二接收机以与差分接收机不同的频率访问协议识别块。

    IO self test method and apparatus for memory
    19.
    发明授权
    IO self test method and apparatus for memory 有权
    IO自检方法和记忆装置

    公开(公告)号：US07519891B2

    公开(公告)日：2009-04-14

    申请号：US11238897

    申请日：2005-09-28

    申请人： David J. Zimmerman

    发明人： David J. Zimmerman

    IPC分类号： G01R31/28

    CPC分类号： G11C29/36 ,  G11C29/022 ,  G11C29/32 ,  G11C2029/0405 ,  G11C2029/3602

    摘要： A memory includes a data generator to generate a data pattern, a transmitter in communication with the data generator, the transmitter to transmit the data pattern as a test data pattern, receiver to receive the test data pattern from the transmitter, and a comparator coupled with the receiver, the comparator to compare the data pattern with the test data pattern from the receiver and to verify proper operation of a memory channel. A method includes providing a seed value to a transmit and a receive pattern generator in a memory, generating data at the transmit pattern generator from the seed value and transmitting the data from the memory, looping the data to a receiver on the memory, using the seed value to generate data with the receive pattern generator, and comparing the data from the receive pattern generator and the transmit pattern generator to determine if any errors occurred.

    摘要翻译： 存储器包括用于生成数据模式的数据发生器，与数据发生器通信的发送器，发送数据模式作为测试数据模式的发送器，从发送器接收测试数据模式的接收器， 接收器，比较器将数据模式与来自接收器的测试数据模式进行比较，并验证存储器通道的正确操作。 一种方法包括向存储器中的发送和接收模式发生器提供种子值，从种子值在发送模式发生器处产生数据并从存储器发送数据，使用数据将数据循环到存储器上的接收器，使用 种子值以与接收模式发生器产生数据，并且比较来自接收模式发生器和发送模式发生器的数据，以确定是否发生任何错误。