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公开(公告)号:US20140333459A1
公开(公告)日:2014-11-13
申请号:US14274813
申请日:2014-05-12
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Takashi OSHIMA , Tatsuji MATSUURA , Yuichi OKUDA , Hideo NAKANE , Takaya YAMAMOTO , Keisuke KIMURA
CPC classification number: H03M1/1033 , H03M1/002 , H03M1/1052 , H03M1/12 , H03M1/201 , H03M1/44 , H03M1/46 , H03M1/66 , H03M1/745
Abstract: To compensate for non-linearity of an AD conversion unit and non-linearity of a DA conversion unit in an electronic system including the DA conversion unit and the AD conversion unit, an electronic system includes an A/D conversion unit, a D/A conversion unit, an AD conversion compensation unit, a DA conversion compensation unit, and a calibration unit. During a calibration operation period, the calibration unit sets an operating characteristic of the AD conversion compensation unit and an operating characteristic of the DA conversion compensation unit. The operating characteristic of the AD conversion compensation unit set during the calibration operation period compensates for non-linearity of AD conversion of the A/D conversion unit. The operating characteristic of the DA conversion compensation unit set during the calibration operation period compensates for non-linearity of DA conversion of the D/A conversion unit.
Abstract translation: 为了补偿包括DA转换单元和AD转换单元的电子系统中的AD转换单元的非线性和DA转换单元的非线性,电子系统包括A / D转换单元,D / A 转换单元,AD转换补偿单元,DA转换补偿单元和校准单元。 在校准操作期间,校准单元设定AD转换补偿单元的工作特性和DA转换补偿单元的工作特性。 在校准操作期间设定的AD转换补偿单元的工作特性补偿A / D转换单元的AD转换的非线性。 在校准操作期间设置的DA转换补偿单元的工作特性补偿D / A转换单元的DA转换的非线性。
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公开(公告)号:US20170201264A1
公开(公告)日:2017-07-13
申请号:US15472866
申请日:2017-03-29
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Keisuke KIMURA , Yuichi OKUDA , Hideo NAKANE , Takaya YAMAMOTO
IPC: H03M1/06 , H03M1/46 , H01L27/06 , H03M1/12 , H01L23/528 , H01L23/522
CPC classification number: H03M1/0607 , H01L23/5225 , H01L23/5226 , H01L23/528 , H01L27/0629 , H01L2924/0002 , H03M1/0604 , H03M1/1023 , H03M1/124 , H03M1/1245 , H03M1/442 , H03M1/46 , H03M1/462 , H03M1/468 , H01L2924/00
Abstract: A semiconductor device according to an aspect of the invention relates to an AD converter that converts a signal level of an analog signal into a digital value by using a comparator, and determines an amount of adjustment of an offset voltage of the comparator based on an offset determination result of the comparator obtained immediately after a least significant bit (LSB) of a digital value output as a conversion result is converted.
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公开(公告)号:US20160294403A1
公开(公告)日:2016-10-06
申请号:US15181877
申请日:2016-06-14
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Keisuke KIMURA , Yuichi OKUDA , Hideo NAKANE , Takaya YAMAMOTO
IPC: H03M1/06 , H03M1/46 , H03M1/12 , H01L23/522 , H01L27/06
CPC classification number: H03M1/0607 , H01L23/5225 , H01L23/5226 , H01L23/528 , H01L27/0629 , H01L2924/0002 , H03M1/0604 , H03M1/1023 , H03M1/124 , H03M1/1245 , H03M1/442 , H03M1/46 , H03M1/462 , H03M1/468 , H01L2924/00
Abstract: A semiconductor device according to an aspect of the invention relates to an AD converter that converts a signal level of an analog signal into a digital value by using a comparator, and determines an amount of adjustment of an offset voltage of the comparator based on an offset determination result of the comparator obtained immediately after a least significant bit (LSB) of a digital value output as a conversion result is converted.
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公开(公告)号:US20160173115A1
公开(公告)日:2016-06-16
申请号:US15051193
申请日:2016-02-23
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Yuichi OKUDA , Hideo NAKANE , Takaya YAMAMOTO , Keisuke KIMURA , Takashi OSHIMA , Tatsuji MATSUURA
CPC classification number: H03M1/1009 , G11C27/02 , H03F1/02 , H03F1/3211 , H03F3/005 , H03F3/45071 , H03F3/45475 , H03F2203/45171 , H03F2203/45544 , H03H7/004 , H03M1/002 , H03M1/124 , H03M1/38 , H03M1/44
Abstract: A differential signal is amplified by passive amplification which does not a reference of a common-mode voltage. At this time, the voltage of the differential signal is passive-amplified twice before carrying out a successive approximation type analog-digital conversion operation. The passive amplification is attained by providing a plurality of capacitances which carry out a sampling operation, and switching these connection relation by using switches. Without being accompanied by the increase of the consumed power and the chip size, an influence by the noise of s comparator is reduced to a half so that the effective resolution can be increased for one bit.
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公开(公告)号:US20150256193A1
公开(公告)日:2015-09-10
申请号:US14711733
申请日:2015-05-13
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Takashi OSHIMA , Tatsuji MATSUURA , Yuichi OKUDA , Hideo NAKANE , Takaya YAMAMOTO , Keisuke KIMURA
CPC classification number: H03M1/1245 , H03M1/002 , H03M1/0609 , H03M1/0639 , H03M1/1038 , H03M1/109 , H03M1/14 , H03M1/38 , H03M1/44 , H03M1/46 , H03M1/56
Abstract: A digital-correction-type A/D converter which is a charge sharing type and performing successive approximation is realized in a small area. The A/D converter is configured with an A/D conversion unit which is a charge sharing type and performing successive approximation, a digital correction unit which receives a digital output of the A/D conversion unit and performs digital correction to the digital output, and a holding unit which holds a test signal. A test signal of a common value from the holding unit is inputted into the A/D conversion unit in the first period and the second period. The A/D conversion correction coefficient for the digital correction unit is calculated on the basis of the digital correction result of the digital correction unit in the first period, and the digital correction result of the digital correction unit in the second period.
Abstract translation: 在小区域中实现了作为电荷共享型并进行逐次逼近的数字校正型A / D转换器。 A / D转换器配置有作为电荷共享型的A / D转换单元并执行逐次逼近,数字校正单元接收A / D转换单元的数字输出并对数字输出执行数字校正, 以及保持测试信号的保持单元。 来自保持单元的公共值的测试信号在第一周期和第二周期中被输入到A / D转换单元。 基于第一周期中的数字校正单元的数字校正结果和第二周期中的数字校正单元的数字校正结果来计算数字校正单元的A / D转换校正系数。
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16.
公开(公告)号:US20150229322A1
公开(公告)日:2015-08-13
申请号:US14692374
申请日:2015-04-21
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Yuichi OKUDA , Hideo NAKANE , Takaya YAMAMOTO , Keisuke KIMURA , Takashi OSHIMA , Tatsuji MATSUURA
CPC classification number: H03M1/1009 , G11C27/02 , H03F1/02 , H03F1/3211 , H03F3/005 , H03F3/45071 , H03F3/45475 , H03F2203/45171 , H03F2203/45544 , H03H7/004 , H03M1/002 , H03M1/124 , H03M1/38 , H03M1/44
Abstract: A differential signal is amplified by passive amplification which does not a reference of a common-mode voltage. At this time, the voltage of the differential signal is passive-amplified twice before carrying out a successive approximation type analog-digital conversion operation. The passive amplification is attained by providing a plurality of capacitances which carry out a sampling operation, and switching these connection relation by using switches. Without being accompanied by the increase of the consumed power and the chip size, an influence by the noise of s comparator is reduced to a half so that the effective resolution can be increased for one bit.
Abstract translation: 差分信号被无源放大放大,其不是共模电压的参考。 此时,在进行逐次逼近型模拟数字转换操作之前,差分信号的电压被无源放大两次。 无源放大通过提供执行采样操作的多个电容来实现,并且通过使用开关来切换这些连接关系。 在不伴随消耗功率和芯片尺寸的增加的情况下,将比较器的噪声的影响减小到一半,使得有效分辨率可以增加一位。
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17.
公开(公告)号:US20150188555A1
公开(公告)日:2015-07-02
申请号:US14579049
申请日:2014-12-22
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Keisuke KIMURA , Yuichi OKUDA , Hideo NAKANE , Takaya YAMAMOTO
CPC classification number: H03M1/0634 , H03M1/002 , H03M1/0617 , H03M1/1009 , H03M1/12 , H03M1/1215 , H03M1/1225
Abstract: An analog-to-digital converter circuit having a simple design and capable of preventing an increase in surface area and other problems. An analog-to-digital converter circuit for converting an analog input signal to a digital quantity includes an analog-to-digital converter unit that converts analog input signals to pre-correction digital values, and a corrector unit that digitally corrects the pre-connection digital values output from the analog-to-digital converter unit. The corrector unit includes a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying the weighting coefficients provided for each bit by each bit of the pre-correction digital value output from the A/D converter unit and summing them, and a weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based on the post-correction digital value and an approximate value for the post-correction digital value.
Abstract translation: 一种具有简单设计并能够防止表面积增加和其他问题的模数转换器电路。 用于将模拟输入信号转换为数字量的模数转换器电路包括将模拟输入信号转换成预校正数字值的模数转换器单元,以及对预连接进行数字校正的校正单元 从模数转换器单元输出的数字值。 校正单元包括加权系数乘法器单元,其输出通过将从每个比特提供的加权系数乘以从A / D转换器单元输出的预校正数字值的每一位并将其相加得到的校正后数字值,以及 加权系数搜索单元,其搜索加权系数,以便最小化基于校正后数字值产生的误差信号和校正后数字值的近似值。
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公开(公告)号:US20150171879A1
公开(公告)日:2015-06-18
申请号:US14487179
申请日:2014-09-16
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Keisuke KIMURA , Yuichi OKUDA , Hideo NAKANE , Takaya YAMAMOTO
CPC classification number: H03M1/0607 , H01L23/5225 , H01L23/5226 , H01L23/528 , H01L27/0629 , H01L2924/0002 , H03M1/0604 , H03M1/1023 , H03M1/124 , H03M1/1245 , H03M1/442 , H03M1/46 , H03M1/462 , H03M1/468 , H01L2924/00
Abstract: A semiconductor device according to an aspect of the invention relates to an AD converter that converts a signal level of an analog signal into a digital value by using a comparator, and determines an amount of adjustment of an offset voltage of the comparator based on an offset determination result of the comparator obtained immediately after a least significant bit (LSB) of a digital value output as a conversion result is converted.
Abstract translation: 根据本发明的一个方面的半导体器件涉及通过使用比较器将模拟信号的信号电平转换为数字值的AD转换器,并且基于偏移来确定比较器的偏移电压的调整量 在作为转换结果的数字值输出的最低有效位(LSB)之后立即获得的比较器的确定结果被转换。
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