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公开(公告)号:US20150060948A1
公开(公告)日:2015-03-05
申请号:US14472665
申请日:2014-08-29
Applicant: Renesas Electronics Corporation
Inventor: Tohru KAWAI , Yutaka AKIYAMA , Yasutaka NAKASHIBA
IPC: H01L29/778 , H01L29/205 , H01L29/201 , H01L29/40 , H01L29/20
CPC classification number: H01L29/404 , H01L29/2003 , H01L29/407 , H01L29/41758 , H01L29/4236 , H01L29/517 , H01L29/66462 , H01L29/7786 , H01L29/7787
Abstract: A field plate causes excessive gate capacitance that interferes with high-speed transistor switching. To suppress the excessive gate capacitance, an aperture includes a first side wall positioned on the side of a drain electrode, and a second side wall positioned on the side of a source electrode. A gate electrode at the same time includes a first side surface facing opposite the drain electrode as seen from a plan view. The first side surface of the gate electrode is positioned on the inner side of the first side wall and the second side wall as seen from a flat view. Moreover, a portion of a first field plate is embedded between the first side surface and the first side wall. The gate electrode and the first field plate are electrically insulated by a first insulation member.
Abstract translation: 场板引起过大的栅极电容干扰高速晶体管切换。 为了抑制过剩的栅极电容,孔包括位于漏极侧的第一侧壁和位于源极侧的第二侧壁。 栅电极同时包括从俯视图看的与漏电极相对的第一侧表面。 从平面看,栅电极的第一侧表面位于第一侧壁和第二侧壁的内侧。 此外,第一场板的一部分嵌入在第一侧面和第一侧壁之间。 栅电极和第一场板由第一绝缘构件电绝缘。
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公开(公告)号:US20250054884A1
公开(公告)日:2025-02-13
申请号:US18932997
申请日:2024-10-31
Applicant: Renesas Electronics Corporation
Inventor: Tohru KAWAI , Yasutaka NAKASHIBA
Abstract: A semiconductor device has a semiconductor substrate, a first insulating layer, a first inductor, a second insulating layer, a second inductor, a pad and an annular wiring. The first insulating layer is formed on the semiconductor substrate. The first inductor is directly formed on the first insulating layer. The second insulating layer is formed on the first insulating layer such that the second insulating layer covers the first inductor. The second inductor is directly formed on the second insulating layer such that the second inductor faces the first inductor. The pad is directly formed on the second insulating layer. The pad is electrically connected with the second inductor. The annular wiring is electrically connected with the pad. The annular wiring is spaced apart from the second inductor. The annular wiring surrounds the second inductor without forming a vertex in plan view.
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公开(公告)号:US20240304524A1
公开(公告)日:2024-09-12
申请号:US18664117
申请日:2024-05-14
Applicant: Renesas Electronics Corporation
Inventor: Tohru KAWAI , Yasutaka NAKASHIBA
IPC: H01L23/485 , H01L29/872
CPC classification number: H01L23/485 , H01L29/872
Abstract: A semiconductor device includes a semiconductor substrate, a buried insulating film, a first conductive film, an insulating layer, a first contact and a second contact. The semiconductor substrate includes a first semiconductor region having a first conductive type and a second semiconductor region having a second conductive type. The buried insulating film surrounds the second semiconductor region in plan view. The first conductive film directly contacts with the first and second semiconductor regions. The first and second contacts overlap with the second semiconductor region in plan view and reach the first conductive film. The first contact is adjacent to the second contact along a first side of the second semiconductor region in plan view. In a direction along the first side, a first distance between the second semiconductor region and the buried insulating film is greater than a second distance between the first contact and the second contact.
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公开(公告)号:US20240170421A1
公开(公告)日:2024-05-23
申请号:US18484982
申请日:2023-10-11
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Teruhiro KUWAJIMA , Tohru KAWAI , Takashi TONEGAWA
IPC: H01L23/00
CPC classification number: H01L24/05 , H01L24/03 , H01L24/06 , H01L2224/0345 , H01L2224/03464 , H01L2224/0391 , H01L2224/05005 , H01L2224/05011 , H01L2224/05013 , H01L2224/05022 , H01L2224/05026 , H01L2224/0508 , H01L2224/05124 , H01L2224/05138 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05186 , H01L2224/05553 , H01L2224/05562 , H01L2224/05571 , H01L2224/05573 , H01L2224/05644 , H01L2224/06135 , H01L2924/01014 , H01L2924/0132 , H01L2924/0133 , H01L2924/04941
Abstract: A pad is formed on an interlayer insulation film, a first insulation film is formed on the interlayer insulation film so as to cover the pad, and a second insulation film is formed on the first insulation film so as to cover the pad. The first insulation film includes a first opening partially exposing the pad, and the second insulation film includes a second opening partially exposing the pad, and the second opening is included in the first opening in plan view. The first insulation film is made of silicon oxide, and the second insulation film is made of silicon nitride or silicon oxynitride. A nickel plating film is formed on the pad exposed from the second opening. A distance from an outer circumference of the pad to an inner wall of the first opening increases in accordance with a thickness of the nickel plating film.
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公开(公告)号:US20230016552A1
公开(公告)日:2023-01-19
申请号:US17946368
申请日:2022-09-16
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Tohru KAWAI , Yasutaka NAKASHIBA
IPC: H01L23/485 , H01L29/872
Abstract: A semiconductor device includes a semiconductor substrate, a buried insulating film, a first conductive film, an insulating layer, a first contact and a second contact. The semiconductor substrate includes a first semiconductor region having a first conductive type and a second semiconductor region having a second conductive type. The buried insulating film surrounds the second semiconductor region in plan view. The first conductive film directly contacts with the first and second semiconductor regions. The first and second contacts overlap with the second semiconductor region in plan view and reach the first conductive film. The first contact is adjacent to the second contact along a first side of the second semiconductor region in plan view. In a direction along the first side, a first distance between the second semiconductor region and the buried insulating film is greater than a second distance between the first contact and the second contact.
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公开(公告)号:US20180090382A1
公开(公告)日:2018-03-29
申请号:US15687444
申请日:2017-08-26
Applicant: Renesas Electronics Corporation
Inventor: Tohru KAWAI
IPC: H01L21/8234 , H01L21/8238 , H01L29/45 , H01L27/06
CPC classification number: H01L21/823418 , H01L21/823481 , H01L21/823814 , H01L21/823835 , H01L27/0629 , H01L27/0922 , H01L28/20 , H01L29/456 , H01L29/665 , H01L29/8605
Abstract: A manufacturing method of a semiconductor device comprises a step of ion-implanting a P-type impurity at a first dose amount to form semiconductor regions that are low concentration semiconductor regions of a high breakdown voltage P-type transistor, and a step of ion-implanting a P-type impurity at a second dose amount to form P− semiconductor regions that are low concentration semiconductor regions of a low breakdown voltage P-type transistor and form a P-type impurity layer that is a resistance portion of a polysilicon resistor. The manufacturing method further comprises a resistance portion forming step in which a resistance portion of the polysilicon resistor is made thinner than terminal portions at both ends of the resistance portion, and the second dose amount is larger than the first dose amount.
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公开(公告)号:US20170125581A1
公开(公告)日:2017-05-04
申请号:US15403539
申请日:2017-01-11
Applicant: Renesas Electronics Corporation
Inventor: Tohru KAWAI , Yasutaka NAKASHIBA , Yutaka AKIYAMA
IPC: H01L29/78 , H01L27/07 , H01L29/06 , H01L29/739 , H01L29/10 , H01L29/423 , H01L23/00 , H01L29/66
CPC classification number: H01L29/7813 , H01L23/4824 , H01L23/4952 , H01L23/49562 , H01L23/5223 , H01L24/05 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L27/0629 , H01L27/0733 , H01L29/0696 , H01L29/1095 , H01L29/4236 , H01L29/66333 , H01L29/66348 , H01L29/66712 , H01L29/66734 , H01L29/7395 , H01L29/7397 , H01L29/7803 , H01L2224/05624 , H01L2224/0603 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/48464 , H01L2224/49111 , H01L2224/73265 , H01L2924/00014 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
Abstract: Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.
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公开(公告)号:US20240136352A1
公开(公告)日:2024-04-25
申请号:US18452834
申请日:2023-08-20
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Natsumi IKEDA , Tohru KAWAI
IPC: H01L27/06 , H01L21/265 , H01L21/266 , H01L21/8234 , H01L29/08 , H01L29/423 , H01L29/66 , H01L29/78
CPC classification number: H01L27/0629 , H01L21/26513 , H01L21/26586 , H01L21/266 , H01L21/823462 , H01L21/823475 , H01L28/20 , H01L29/0847 , H01L29/42364 , H01L29/66492 , H01L29/7833
Abstract: A semiconductor device including an oscillation circuit includes a MISFET having a halo region formed on a semiconductor substrate and a plurality of MISFETs having no halo regions formed on the semiconductor substrate. Gate electrodes of the plurality of MISFETs having no halo regions are electrically connected to each other. The plurality of MISFETs having no halo regions is used in a pair transistor included in the oscillation circuit.
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公开(公告)号:US20230299197A1
公开(公告)日:2023-09-21
申请号:US17697393
申请日:2022-03-17
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Eiji TSUKUDA , Tohru KAWAI , Atsushi AMO
CPC classification number: H01L29/78391 , H01L29/516
Abstract: A semiconductor device is provided with an SOI substrate which includes a semiconductor substrate, a ferroelectric layer and a semiconductor layer, and has a first region in which a first MISFET is formed. The first MISFET includes: the semiconductor substrate in the first region; the ferroelectric layer in the first region; the semiconductor layer in the first region; a first gate insulating film formed on the semiconductor layer in the first region; a first gate electrode formed on the first gate insulating film; a first source region located on one side of the first gate electrode and formed in the semiconductor layer in the first region; and a first drain region located on the other side of the first gate electrode and formed in the semiconductor layer in the first region.
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公开(公告)号:US20220173056A1
公开(公告)日:2022-06-02
申请号:US17108298
申请日:2020-12-01
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Tohru KAWAI , Yasutaka NAKASHIBA
Abstract: A semiconductor device has a semiconductor substrate, a first insulating layer, a first inductor, a second insulating layer, a second inductor, a pad and an annular wiring. The first insulating layer is formed on the semiconductor substrate. The first inductor is directly formed on the first insulating layer. The second insulating layer is formed on the first insulating layer such that the second insulating layer covers the first inductor. The second inductor is directly formed on the second insulating layer such that the second inductor faces the first inductor. The pad is directly formed on the second insulating layer. The pad is electrically connected with the second inductor. The annular wiring is electrically connected with the pad. The annular wiring is spaced apart from the second inductor. The annular wiring surrounds the second inductor without forming a vertex in plan view.
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