公开(公告)号：US09252262B2

公开(公告)日：2016-02-02

申请号：US14590937

申请日：2015-01-06

Applicant: Renesas Electronics Corporation

Inventor： Satoshi Eguchi ,  Yoshito Nakazawa

IPC: H01L29/12 ,  H01L29/38 ,  H01L29/739 ,  H01L29/78 ,  H01L29/861 ,  H01L29/06 ,  H01L29/165 ,  H01L29/16 ,  H01L21/265 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L21/761 ,  H01L21/0415 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7811 ,  H01L29/861

Abstract: The reliability of a semiconductor device including a power semiconductor element is improved. The basic idea in embodiments is to make the band gap of a cell region smaller than the band gap of a peripheral region. Specifically, a lower band gap region having a smaller band gap than the band gap of an epitaxial layer is formed in the cell region. In addition, a higher band gap region having a larger band gap than the band gap of the epitaxial layer is formed in the peripheral region.

Abstract translation: 提高了包括功率半导体元件的半导体器件的可靠性。 实施例中的基本思想是使单元区域的带隙小于外围区域的带隙。 具体地，在单元区域中形成具有比外延层的带隙小的带隙的较低带隙区域。 此外，在周边区域中形成具有比外延层的带隙大的带隙的较高带隙区域。

公开(公告)号：US09245973B2

公开(公告)日：2016-01-26

申请号：US14690783

申请日：2015-04-20

Applicant: Renesas Electronics Corporation

Inventor： Yoshito Nakazawa ,  Yuji Yatsuda

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/78 ,  H01L21/28 ,  H01L21/285 ,  H01L29/49 ,  H01L27/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45

CPC classification number: H01L29/7808 ,  H01L21/28008 ,  H01L21/28556 ,  H01L27/0255 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

Abstract: A method for manufacturing a semiconductor device having a field-effect transistor, including forming a trench in a semiconductor substrate, forming a first insulating film in the trench, forming an intrinsic polycrystalline silicon film over the first insulating film, and introducing first conductive type impurities into the intrinsic polycrystalline silicon film to form a first conductive film. The first conductive film is etched to form a first gate electrode in the trench. Next, a second insulating film is formed in the trench above the first insulating film and the first gate electrode, and a first conductivity type doped polycrystalline silicon film, having higher impurity concentration than the first gate electrode is formed over the second insulating film. The doped polycrystalline silicon film, upper part of the trench ton form a second gate electrode.

公开(公告)号：US08659078B2

公开(公告)日：2014-02-25

申请号：US13792134

申请日：2013-03-10

Applicant: Renesas Electronics Corporation

Inventor： Hitoshi Matsuura ,  Yoshito Nakazawa ,  Tsuyoshi Kachi ,  Yuji Yatsuda

IPC: H01L27/108 ,  H01L29/78

CPC classification number: H01L27/0629 ,  H01L21/26586 ,  H01L21/76897 ,  H01L29/0615 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8725

Abstract: A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.

Abstract translation: 栅极沟槽13形成在半导体衬底10中。栅极沟槽13设置有形成在栅极绝缘膜14上的栅电极16.栅电极16的一部分从半导体衬底10突出，侧壁24为 形成在突出部分的侧壁部分上。 形成与相邻的栅电极16对准的主体沟槽25.在栅电极16的表面上并在主体沟槽25的表面之上形成硅化钴膜28.使用SAC技术形成插塞34。

公开(公告)号：US11107912B2

公开(公告)日：2021-08-31

申请号：US16272601

申请日：2019-02-11

Applicant: Renesas Electronics Corporation

Inventor： Yoshito Nakazawa ,  Yuji Yatsuda

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L27/02 ,  H01L21/28 ,  H01L21/285 ,  H01L29/49 ,  H01L29/45

Abstract: A semiconductor device including a field-effect transistor having source and drain source regions, first and second gate electrodes and a protective diode connected to the transistor. The first gate electrode is formed over a first gate insulating film in a lower part of a trench. The second gate electrode is formed over a second gate insulating film in an upper part of the trench. The first gate electrode includes a first polysilicon film, and the second gate electrode includes a second polysilicon film, wherein an impurity concentration of the first polysilicon film is lower than an impurity concentration of the second polysilicon film.

公开(公告)号：US09825167B2

公开(公告)日：2017-11-21

申请号：US15236678

申请日：2016-08-15

Applicant: Renesas Electronics Corporation

Inventor： Hitoshi Matsuura ,  Yoshito Nakazawa

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/49

CPC classification number: H01L29/7813 ,  H01L29/0619 ,  H01L29/407 ,  H01L29/4983 ,  H01L29/78

Abstract: In characteristic test measurements of double-gate-in-trench p-channel power MOSFETs each having a p+ polysilicon gate electrode and a p+ field plate electrode in a trench, which were fabricated according to common design techniques, it has been found that, under conditions where a negative gate bias is applied continuously at high temperature with respect to the substrate, an absolute value of threshold voltage tends to increase steeply after the lapse of a certain period of stress application time. To solve this problem, the present invention provides a p-channel power MOSFET having an n-type polysilicon linear field plate electrode and an n-type polysilicon linear gate electrode in each trench part thereof.

公开(公告)号：US09478530B2

公开(公告)日：2016-10-25

申请号：US15001767

申请日：2016-01-20

Applicant: Renesas Electronics Corporation

Inventor： Yoshito Nakazawa ,  Yuji Yatsuda

IPC: H01L27/02 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L21/285 ,  H01L29/49 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45

CPC classification number: H01L29/7808 ,  H01L21/28008 ,  H01L21/28556 ,  H01L27/0255 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

Abstract: A semiconductor device having a field-effect transistor, including a trench in a semiconductor substrate, a first insulating film in the trench, an intrinsic polycrystalline silicon film over the first insulating film, and first conductivity type impurities in the intrinsic polycrystalline silicon film to form a first conductive film. The first conductive film is etched to form a first gate electrode in the trench. A second insulating film is also formed in the trench above the first insulating film and the first gate electrode, and a first conductivity type doped polycrystalline silicon film, having higher impurity concentration than the first gate electrode is formed over the second insulating film. The doped polycrystalline silicon film is provided in an upper part of the trench to form a second gate electrode.

Abstract translation: 一种具有场效应晶体管的半导体器件，包括半导体衬底中的沟槽，沟槽中的第一绝缘膜，第一绝缘膜上的本征多晶硅膜，以及本征多晶硅膜中的第一导电型杂质，以形成 第一导电膜。 蚀刻第一导电膜以在沟槽中形成第一栅电极。 在第二绝缘膜上形成有在第一绝缘膜和第一栅电极上方的沟槽中的第二绝缘膜，并且在第二绝缘膜上形成杂质浓度高于第一栅电极的第一导电型掺杂多晶硅膜。 掺杂多晶硅膜设置在沟槽的上部，以形成第二栅电极。

公开(公告)号：US09349827B2

公开(公告)日：2016-05-24

申请号：US14718695

申请日：2015-05-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hitoshi Matsuura ,  Makoto Koshimizu ,  Yoshito Nakazawa

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/36 ,  H01L29/739 ,  H01L29/861 ,  H01L29/08 ,  H01L29/10 ,  H01L21/265 ,  H01L29/16

CPC classification number: H01L29/66348 ,  H01L21/265 ,  H01L29/0615 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/7397 ,  H01L29/8611

Abstract: In an IGBT, defects generated by ion implantation for introduction of the P-type collector region or N-type buffer region into the N−-type drift region near the N-type buffer region remain to improve the switching speed, however the leak current increases by bringing a depletion layer into contact with the crystal defects at the off time. To avoid this, an IGBT is provided which includes an N-type buffer region having a higher concentration than that of an N−-type drift region and being in contact with a P-type on its backside, and a defect remaining region provided near the boundary between the N-type buffer region and the N−-type drift region. The N−-type drift region located on the front surface side with respect to the defect remaining region is provided with an N-type field stopping region having a higher concentration than that of the N−-type drift region.

公开(公告)号：US20150287778A1

公开(公告)日：2015-10-08

申请号：US14743897

申请日：2015-06-18

Applicant: Renesas Electronics Corporation

Inventor： Tomohiro Tamaki ,  Yoshito Nakazawa ,  Satoshi Eguchi

IPC: H01L29/06 ,  H01L29/739 ,  H01L29/78 ,  H01L29/10 ,  H01L29/40

CPC classification number: H01L29/7811 ,  H01L27/088 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/6634 ,  H01L29/66727 ,  H01L29/7395 ,  H01L29/7396

Abstract: A semiconductor device which solves the following problem of a super junction structure: due to a relatively high concentration in the body cell region (active region), in peripheral areas (peripheral regions or junction end regions), it is difficult to achieve a breakdown voltage equivalent to or higher than in the cell region through a conventional junction edge terminal structure or resurf structure. The semiconductor device includes a power MOSFET having a super junction structure formed in the cell region by a trench fill technique. Also, super junction structures having orientations parallel to the sides of the cell region are provided in a drift region around the cell region.

Abstract translation: 解决超结结构的以下问题的半导体装置：由于体细胞区域（有源区域）的相对高的浓度，在周边区域（周边区域或结合区域）中难以实现击穿电压 等于或高于通过常规的连接边缘端子结构或再结构的单元区域。 半导体器件包括通过沟槽填充技术在单元区域中形成的具有超结结构的功率MOSFET。 此外，在细胞区域周围的漂移区域中设置具有与细胞区域的侧面平行的取向的超结结构。

公开(公告)号：US09093288B2

公开(公告)日：2015-07-28

申请号：US14309651

申请日：2014-06-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tomohiro Tamaki ,  Yoshito Nakazawa ,  Satoshi Eguchi

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L27/088 ,  H01L29/10 ,  H01L29/417

CPC classification number: H01L29/7811 ,  H01L27/088 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/6634 ,  H01L29/66727 ,  H01L29/7395 ,  H01L29/7396

Abstract: A semiconductor device which solves the following problem of a super junction structure: due to a relatively high concentration in the body cell region (active region), in peripheral areas (peripheral regions or junction end regions), it is difficult to achieve a breakdown voltage equivalent to or higher than in the cell region through a conventional junction edge terminal structure or resurf structure. The semiconductor device includes a power MOSFET having a super junction structure formed in the cell region by a trench fill technique. Also, super junction structures having orientations parallel to the sides of the cell region are provided in a drift region around the cell region.

Abstract translation: 解决超结结构的以下问题的半导体装置：由于体细胞区域（有源区域）的相对高的浓度，在周边区域（周边区域或结合区域）中难以实现击穿电压 等于或高于通过常规的连接边缘端子结构或再结构的单元区域。 半导体器件包括通过沟槽填充技术在单元区域中形成的具有超结结构的功率MOSFET。 此外，在细胞区域周围的漂移区域中设置具有与细胞区域的侧面平行的取向的超结结构。

公开(公告)号：US09013006B2

公开(公告)日：2015-04-21

申请号：US14100462

申请日：2013-12-09

Applicant: Renesas Electronics Corporation

Inventor： Yoshito Nakazawa ,  Yuji Yatsuda

IPC: H01L27/088 ,  H01L21/28 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L27/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45

CPC classification number: H01L29/7808 ,  H01L21/28008 ,  H01L21/28556 ,  H01L27/0255 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

Abstract: A method for manufacturing a semiconductor device having a field-effect transistor, including forming a trench in a semiconductor substrate, forming a first insulating film in the trench, forming an intrinsic polycrystalline silicon film over the first insulating film, and introducing first conductive type impurities into the intrinsic polycrystalline silicon film to form a first conductive film. The first conductive film is etched to form a first gate electrode in the trench. Next, a second insulating film is formed in the trench above the first insulating film and the first gate electrode, anda first conductivity type doped polycrystalline silicon film, having higher impurity concentration than the first gate electrode is formed over the second insulating film. The doped polycrystalline silicon film, upper part of the trench ton form a second gate electrode.

Abstract translation: 一种制造具有场效应晶体管的半导体器件的方法，包括在半导体衬底中形成沟槽，在沟槽中形成第一绝缘膜，在第一绝缘膜上形成本征多晶硅膜，并引入第一导电类型杂质 进入本征多晶硅膜以形成第一导电膜。 蚀刻第一导电膜以在沟槽中形成第一栅电极。 接下来，在第二绝缘膜上形成第二绝缘膜，该第二绝缘膜形成在第一绝缘膜和第一栅电极之上的沟槽中，并且在第二绝缘膜上形成杂质浓度高于第一栅电极的第一导电型掺杂多晶硅膜。 掺杂多晶硅膜，沟槽ton的上部形成第二栅电极。