公开(公告)号：US11296219B2

公开(公告)日：2022-04-05

申请号：US16827150

申请日：2020-03-23

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Senichirou Nagase ,  Tsuyoshi Kachi ,  Yoshinori Hoshino

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/10 ,  H01L29/40

Abstract: In a deep trench DTC reaching a predetermined depth from a first main surface of a semiconductor substrate SUB, a plurality of columnar conductors CCB including plugs PUG and field plates FP are formed. A p type impurity layer PIL is formed along the side wall surface of the deep trench DTC. Between the bottom of the plug PUG and the bottom of the p type impurity layer PIL, the field plate FP and the p type impurity layer PIL are positioned to face each other via an insulating film FIF interposed therebetween. Between the bottom of the p type impurity layer PIL and the bottom of the field plate FP, the field plate FP and an n-type drift layer NDL of the semiconductor substrate SUB are positioned to face each other via the insulating film FIF interposed therebetween.

公开(公告)号：US09406787B2

公开(公告)日：2016-08-02

申请号：US14806115

申请日：2015-07-22

Applicant: Renesas Electronics Corporation

Inventor： Yuta Ikegami ,  Tsuyoshi Kachi

IPC: H01L29/739 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/66348 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/32105 ,  H01L21/76895 ,  H01L21/8222 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/6634 ,  H01L29/7397

Abstract: An improvement is achieved in the performance of a semiconductor device. Over the main surface of a semiconductor substrate for the n-type base of an IGBT, an insulating layer is formed. In a trench of the insulating layer, an n-type semiconductor layer is formed over the semiconductor substrate and, on both sides of the semiconductor layer, gate electrodes are formed via gate insulating films. In an upper portion of the semiconductor layer, a p-type semiconductor region for a p-type base and an n+-type semiconductor region for an n-type emitter are formed. Under the gate electrodes, parts of the insulating layer are present. The side surfaces of the gate electrodes opposite to the side surfaces thereof facing the semiconductor layer via the gate insulating films are adjacent to the insulating layer.

Abstract translation: 在半导体器件的性能方面实现了改进。 在IGBT的n型基极用半导体基板的主表面上形成绝缘层。 在绝缘层的沟槽中，在半导体衬底上形成n型半导体层，并且在半导体层的两侧，通过栅极绝缘膜形成栅电极。 在半导体层的上部形成p型基极的p型半导体区域和n型发射极的n +型半导体区域。 在栅电极下方存在绝缘层的部分。 与通过栅极绝缘膜面对半导体层的侧表面相对的栅电极的侧表面与绝缘层相邻。

公开(公告)号：US09397156B2

公开(公告)日：2016-07-19

申请号：US14951124

申请日：2015-11-24

Applicant: Renesas Electronics Corporation

Inventor： Tsuyoshi Kachi

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/66 ,  H01L21/265 ,  H01L21/225 ,  H01L21/324

CPC classification number: H01L29/0634 ,  H01L21/225 ,  H01L21/26586 ,  H01L21/324 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

Abstract: To realize a semiconductor device having a power MOSFET satisfying both a low conduction resistance and a high junction breakdown voltage by a simple and easy manufacturing method. Over an n-type substrate, a p-type epitaxial layer of a low concentration is formed, and, in an active part, a plurality of active regions is defined by a plurality of trenches that is formed in the epitaxial layer and extends in a first direction with first intervals in a second direction orthogonal to the first direction. In the epitaxial layer between the adjacent trenches, an n-type diffusion region that functions as a drain offset layer is formed, and, in the epitaxial layer between a side wall of the trench and the n-type diffusion region, a p-type diffusion region connected with a channel region (the p-type diffusion region) is formed, to constitute a super junction structure. Further, by forming an n-type diffusion region in the epitaxial layer, having a prescribed width from a side wall of a trench lying in the end part of the active part toward an outer periphery part, to achieve the improvement of a drain breakdown voltage.

公开(公告)号：US09142555B2

公开(公告)日：2015-09-22

申请号：US14548311

申请日：2014-11-20

Applicant: Renesas Electronics Corporation

Inventor： Yoshinori Yoshida ,  Hirokazu Kato ,  Tsuyoshi Kachi ,  Keisuke Furuya

IPC: H01L29/66 ,  H01L27/088 ,  H01L23/528 ,  H01L29/417 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L29/0696 ,  H01L23/4824 ,  H01L23/49524 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/528 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L27/088 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/4175 ,  H01L29/4238 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92247 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Provided is a semiconductor device having improved performance. A semiconductor substrate is formed with unit LDMOSFET elements. The unit LDMOSFET elements have respective source regions electrically coupled to each other via a first source interconnect line and a second source interconnect line. The unit LDMOSFET elements have respective gate electrodes electrically coupled to each other via a first gate interconnect line and also electrically coupled to a second gate interconnect line in the same layer as that of the second source interconnect line via the first gate interconnect line. The unit LDMOSFET elements have respective drain regions electrically coupled to a back surface electrode via a conductive plug embedded in a trench of the semiconductor substrate. Each of the first source interconnect line and the first gate interconnect line has a thickness smaller than that of the second source interconnect line. Over the plug, the first gate interconnect line extends.

Abstract translation: 提供了具有改进的性能的半导体器件。 半导体衬底由单元LDMOSFET元件形成。 单元LDMOSFET元件具有经由第一源互连线和第二源互连线彼此电耦合的相应源极区域。 单元LDMOSFET元件具有经由第一栅极互连线彼此电耦合的相应栅电极，并且还经由第一栅极互连线电耦合到与第二源极互连线的层相同的层中的第二栅极互连线。 单元LDMOSFET元件具有通过嵌入在半导体衬底的沟槽中的导电插塞电耦合到背面电极的各自的漏极区域。 第一源极互连线和第一栅极互连线中的每一个具有比第二源极互连线的厚度小的厚度。 通过插头，第一个栅极互连线延伸。

公开(公告)号：US10727105B2

公开(公告)日：2020-07-28

申请号：US15592241

申请日：2017-05-11

Applicant: Renesas Electronics Corporation

Inventor： Tsuyoshi Kachi ,  Yoshinori Hoshino ,  Senichirou Nagase

IPC: H01L21/762 ,  H01L21/265 ,  H01L29/423 ,  H01L29/06 ,  H01L29/861 ,  H01L29/66 ,  H01L29/15 ,  H01L29/739 ,  H01L29/78

Abstract: Provided are a semiconductor device and a manufacturing method therefor that can prevent the breakage of an element and in which the control of impurity amounts is less susceptible to variations in manufacturing processes. A semiconductor substrate has a front surface and includes hole portions extending from the front surface to an inside of the substrate. N-type regions are formed in the semiconductor substrate. At wall surfaces of the hole portions, p-type regions are formed to configure p-n junction with the n-type regions. Each of the p-type regions includes a low-concentration region and a high-concentration region formed at the wall surface of each hole portion. A width of the high-concentration region along the wall surface of the hole portion becomes smaller from the front surface toward a deeper position.

公开(公告)号：US10164087B2

公开(公告)日：2018-12-25

申请号：US15428350

申请日：2017-02-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Senichirou Nagase ,  Tsuyoshi Kachi ,  Yoshinori Hoshino

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66 ,  H01L21/265

Abstract: To provide a semiconductor device equipped with a snubber portion having an improved withstand voltage and capable of reducing a surge voltage at turn-off of an insulated gate field effect transistor portion. The concentration of a first conductivity type impurity in a snubber semiconductor region is greater than that in a drift layer. The thickness of a snubber insulating film between the snubber semiconductor region and a snubber electrode is greater than that of a gate insulating film between a gate electrode and a body region.

公开(公告)号：US20150179762A1

公开(公告)日：2015-06-25

申请号：US14635300

申请日：2015-03-02

Applicant: Renesas Electronics Corporation

Inventor： Koichiro Sakanishi ,  Tsuyoshi Kachi ,  Koji Fujishima

IPC: H01L29/66 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/49 ,  H01L21/28

CPC classification number: H01L29/66681 ,  H01L21/28079 ,  H01L21/32134 ,  H01L21/76841 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/66325 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/7811

Abstract: A general insulated gate power semiconductor active element with many gate electrodes arranged in parallel has a laminated structure including a barrier metal film and a thick aluminum electrode film formed over the gate electrodes via an interlayer insulating film. When the aluminum electrode film is embedded in between the gate electrodes in parallel, voids may be generated with the electrodes. Such voids allow the etchant to penetrate in wet etching, which may promote the etching up to a part of the electrode film in an active cell region which is to be left. Thus, an insulated gate power semiconductor device is provided to include gate electrodes protruding outward from the inside of the active cell region, and a gate electrode coupling portion for coupling the gate electrodes outside the active cell region. The gate electrode coupling portion is covered with a metal electrode covering the active cell region.

Abstract translation: 具有并联布置的多个栅极的通用绝缘栅功率半导体有源元件具有通过层间绝缘膜形成在栅电极上的阻挡金属膜和厚铝电极膜的层叠结构。 当铝电极膜平行地嵌入在栅电极之间时，可能产生与电极的空隙。 这样的空隙允许蚀刻剂在湿蚀刻中渗透，这可以促进蚀刻到要留下的活性单元区域中的电极膜的一部分。 因此，提供了一种绝缘栅功率半导体器件，其包括从有源电池区域的内部向外突出的栅极电极和用于将栅电极连接到有源电池区域外部的栅电极耦合部分。 栅极电极耦合部分被覆盖有源电池区域的金属电极覆盖。

公开(公告)号：US10749026B2

公开(公告)日：2020-08-18

申请号：US16116598

申请日：2018-08-29

Applicant: Renesas Electronics Corporation

Inventor： Yoshinori Yoshida ,  Tsuyoshi Kachi

IPC: H01L29/78 ,  H01L29/08 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06

Abstract: Provided are a semiconductor device including a desired snubber part in accordance with use of the semiconductor device and a method of manufacturing the semiconductor device. A snubber region having a snubber part is defined in a gate pad region defined on a side close to a first main surface of a semiconductor substrate. A p-type diffusion layer and an n-type column layer contacted to each other are formed in the snubber region. The p-type diffusion layer and the n-type column layer are formed as a parasitic capacitance of the snubber part while the n-type column layer is electrically coupled to a drain. The p-type diffusion layer, which extends in a Y-axis direction, is a resistance of the snubber part and electrically coupled to a source.

公开(公告)号：US09780187B2

公开(公告)日：2017-10-03

申请号：US15198395

申请日：2016-06-30

Applicant: Renesas Electronics Corporation

Inventor： Yuta Ikegami ,  Tsuyoshi Kachi

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/739 ,  H01L29/10 ,  H01L21/8222 ,  H01L21/768 ,  H01L21/308 ,  H01L21/306 ,  H01L21/321

CPC classification number: H01L29/66348 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/32105 ,  H01L21/76895 ,  H01L21/8222 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/6634 ,  H01L29/7397

Abstract: An improvement is achieved in the performance of a semiconductor device. Over the main surface of a semiconductor substrate for the n-type base of an IGBT, an insulating layer is formed. In a trench of the insulating layer, an n-type semiconductor layer is formed over the semiconductor substrate and, on both sides of the semiconductor layer, gate electrodes are formed via gate insulating films. In an upper portion of the semiconductor layer, a p-type semiconductor region for a p-type base and an n+-type semiconductor region for an n-type emitter are formed. Under the gate electrodes, parts of the insulating layer are present. The side surfaces of the gate electrodes opposite to the side surfaces thereof facing the semiconductor layer via the gate insulating films are adjacent to the insulating layer.

公开(公告)号：US20160079352A1

公开(公告)日：2016-03-17

申请号：US14951124

申请日：2015-11-24

Applicant: Renesas Electronics Corporation

Inventor： Tsuyoshi Kachi

IPC: H01L29/06 ,  H01L21/324 ,  H01L21/225 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/0634 ,  H01L21/225 ,  H01L21/26586 ,  H01L21/324 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

Abstract: To realize a semiconductor device having a power MOSFET satisfying both a low conduction resistance and a high junction breakdown voltage by a simple and easy manufacturing method. Over an n-type substrate, a p-type epitaxial layer of a low concentration is formed, and, in an active part, a plurality of active regions is defined by a plurality of trenches that is formed in the epitaxial layer and extends in a first direction with first intervals in a second direction orthogonal to the first direction. In the epitaxial layer between the adjacent trenches, an n-type diffusion region that functions as a drain offset layer is formed, and, in the epitaxial layer between a side wall of the trench and the n-type diffusion region, a p-type diffusion region connected with a channel region (the p-type diffusion region) is formed, to constitute a super junction structure. Further, by forming an n-type diffusion region in the epitaxial layer, having a prescribed width from a side wall of a trench lying in the end part of the active part toward an outer periphery part, to achieve the improvement of a drain breakdown voltage.

Abstract translation: 通过简单且容易的制造方法实现具有满足低导通电阻和高结击穿电压的功率MOSFET的半导体器件。 在n型衬底上形成低浓度的p型外延层，并且在有源部分中，多个有源区由形成在外延层中的多个沟槽限定，并且在 第一方向在与第一方向正交的第二方向上具有第一间隔。 在相邻沟槽之间的外延层中，形成用作漏极偏移层的n型扩散区，并且在沟槽的侧壁和n型扩散区之间的外延层中，形成p型 形成与沟道区域（p型扩散区域）连接的扩散区域，构成超结构结构。 此外，通过在外延层中形成具有规定宽度的n型扩散区，从位于有源部的端部的沟槽的侧壁朝向外周部，具有规定的宽度，以实现漏极击穿电压的提高 。