公开(公告)号：US06720642B1

公开(公告)日：2004-04-13

申请号：US09464885

申请日：1999-12-16

申请人： Rajeev Joshi ,  Consuelo N. Tangpuz ,  Romel N. Manatad

发明人： Rajeev Joshi ,  Consuelo N. Tangpuz ,  Romel N. Manatad

IPC分类号： H01L23495

CPC分类号： H01L23/49562 ,  H01L23/3121 ,  H01L23/3185 ,  H01L23/49531 ,  H01L23/544 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/00

摘要： A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.

摘要翻译： 一种芯片器件，包括引线框架，模具和模具化合物。 模具的背面被金属化并且通过在模具化合物中限定的窗口暴露，当模具化合物耦合到引线框架时封装模具。 引线框架上的引线耦合到管芯上的源极和栅极端子，而管芯的金属化背面用作漏极端子。

公开(公告)号：US06989588B2

公开(公告)日：2006-01-24

申请号：US09963049

申请日：2001-09-24

申请人： Maria C. Y. Quinones ,  Consuelo N. Tangpuz

发明人： Maria C. Y. Quinones ,  Consuelo N. Tangpuz

IPC分类号： H01L23/02 ,  H01L23/495

CPC分类号： H01L23/49562 ,  H01L24/37 ,  H01L24/40 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/45144 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device including a leadframe and a die coupled thereto. A drain pad is coupled to the drain region of the die in a body that substantially envelopes the leadframe and the die. The body includes a window defined therein. The body is placed around the leadframe and the die such that a surface of the drain pad opposite the die is exposed through the window.

公开(公告)号：US06943434B2

公开(公告)日：2005-09-13

申请号：US10678010

申请日：2003-10-02

申请人： Consuelo N. Tangpuz ,  Romel N. Manatad ,  Margie T. Rios ,  Erwin Victor R. Cruz

发明人： Consuelo N. Tangpuz ,  Romel N. Manatad ,  Margie T. Rios ,  Erwin Victor R. Cruz

IPC分类号： H01L21/60 ,  H01L23/31 ,  H01L23/485 ,  H01L23/495 ,  H01L23/544

CPC分类号： H01L23/49582 ,  H01L23/3107 ,  H01L23/49562 ,  H01L23/49586 ,  H01L23/544 ,  H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18301 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/81205 ,  H01L2224/05599

摘要： A packaging assembly for semiconductor devices and a method for making such packaging is described. The invention provides a non-Pb bump design during a new flip-chip method of packaging. The design uses special conductive materials in a stud form, rather than a solder ball containing Pb. This configuration maintains a desirable solder thickness between the die and the leadframe and forms a high standoff by restricting solder wettabilty on the leadframe side. This configuration also absorbs any stress and protects the die from cracking. The invention also provides methods for making such semiconductor packages.

摘要翻译： 描述了一种用于半导体器件的封装组件及其制造方法。 本发明在新的倒装芯片封装方法中提供了非Pb凸点设计。 该设计采用螺柱形式的特殊导电材料，而不是含Pb的焊球。 该配置在管芯和引线框架之间保持期望的焊料厚度，并通过限制引线框架侧上的焊料润湿性而形成高的间隙。 这种结构也吸收任何应力并保护模具免受开裂。 本发明还提供了制造这种半导体封装的方法。

公开(公告)号：US20110095417A1

公开(公告)日：2011-04-28

申请号：US12607294

申请日：2009-10-28

申请人： Jocel P. Gomez ,  Consuelo N. Tangpuz

发明人： Jocel P. Gomez ,  Consuelo N. Tangpuz

IPC分类号： H01L23/498

CPC分类号： H01L23/3114 ,  H01L21/561 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/13147 ,  H01L2224/94 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/03 ,  H01L2924/00

摘要： This document discusses, among other things, a semiconductor die having a first conductive bump coupled to a first electrical terminal at a first die surface of a semiconductor die and a dielectric substantially covering the first die surface and substantially surrounding the first conductive bump. A surface of the dielectric can include a recessed terminal area, and a second electrical terminal can be coupled to the first conductive bump in the recessed terminal area.

摘要翻译： 本文件尤其涉及一种半导体管芯，该半导体管芯具有耦合到半导体管芯的第一管芯表面处的第一电端子的第一导电凸块和基本上覆盖第一管芯表面并且基本上围绕第一导电凸块的电介质。 电介质的表面可以包括凹入的端子区域，并且第二电端子可以耦合到凹入端子区域中的第一导电凸块。

公开(公告)号：US06423623B1

公开(公告)日：2002-07-23

申请号：US09141184

申请日：1998-08-27

申请人： Izak Bencuya ,  Maria Christina B. Estacio ,  Steven P. Sapp ,  Consuelo N. Tangpuz ,  Gilmore S. Baje ,  Rey D. Maligro

发明人： Izak Bencuya ,  Maria Christina B. Estacio ,  Steven P. Sapp ,  Consuelo N. Tangpuz ,  Gilmore S. Baje ,  Rey D. Maligro

IPC分类号： H01L2144

CPC分类号： H01L24/06 ,  H01L23/49562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/16245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49111 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A packaging technique that significantly reduces package resistance. According to the invention, lead frames external to the package are brought in direct contact to solder balls on the surface of the silicon die inside the package molding, eliminating resistive wire interconnections. The packaging technique of the present invention is particularly suitable for power transistors.

摘要翻译： 一种显着降低封装电阻的封装技术。 根据本发明，封装外部的引线框架与封装模制件内的硅芯片表面上的焊球直接接触，消除了电阻线互连。 本发明的封装技术特别适用于功率晶体管。