公开(公告)号：US07547561B2

公开(公告)日：2009-06-16

申请号：US11281997

申请日：2005-11-17

申请人： Uwe Schulze ,  Martin Mazur ,  Andreas Becker

发明人： Uwe Schulze ,  Martin Mazur ,  Andreas Becker

IPC分类号： H01L21/66 ,  H01L21/312 ,  H01L21/47

CPC分类号： H01L22/20 ,  Y10S430/136

摘要： An advanced process control (APC) architecture comprising a process model that incorporates a target offset term is provided. The APC architecture may be applied to a so-called develop inspect critical dimension (DICD) model using the target offset term to correct at least one exposure parameter on the occurrence of an abrupt event. A corresponding event may, for example, concern a modified reflectivity of processed substrates, for example due to a rework of substrates covered by amorphous carbon material.

摘要翻译： 提供了包括包含目标偏移项的过程模型的高级过程控制（APC）架构。 APC架构可以应用于所谓的开发检查关键维度（DICD）模型，使用目标偏移项来校正突发事件发生时的至少一个曝光参数。 相应的事件例如可能涉及经处理的基板的改进的反射率，例如由于由无定形碳材料覆盖的基板的返修。

公开(公告)号：US06649525B1

公开(公告)日：2003-11-18

申请号：US10050485

申请日：2002-01-16

申请人： Khoi A. Phan ,  Jeffrey Erhardt ,  Jerry Cheng ,  Richard J. Bartlett ,  Anthony P. Coniglio ,  Wolfram Grundke ,  Carol M. Bradway ,  Daniel E. Sutton ,  Martin Mazur

发明人： Khoi A. Phan ,  Jeffrey Erhardt ,  Jerry Cheng ,  Richard J. Bartlett ,  Anthony P. Coniglio ,  Wolfram Grundke ,  Carol M. Bradway ,  Daniel E. Sutton ,  Martin Mazur

IPC分类号： H01L21461

CPC分类号： G03F7/16 ,  G03F7/30 ,  G03F7/40 ,  H01L21/0274 ,  H01L21/32139

摘要： Methods and systems are disclosed for reducing resist residue defects in a semiconductor manufacturing process. The methods comprise appropriate adjustment of hardware, substrate, resist, developer, and process variables in order to remove resist residues from a semiconductor substrate structure in order to reduce resist residue defects therein. The method may comprise employing an anti reflective coating prior to applying a photo resist coating in a semiconductor manufacturing process. Also disclosed are methodologies for exhausting resist residue during development via a rinsing fluid.

摘要翻译： 公开了用于减少半导体制造工艺中的抗蚀剂残留缺陷的方法和系统。 这些方法包括硬件，衬底，抗蚀剂，显影剂和工艺变量的适当调整，以便从半导体衬底结构去除抗蚀剂残留物，以减少其中的抗蚀剂残留缺陷。 该方法可以包括在半导体制造工艺中施加光致抗蚀剂涂层之前采用抗反射涂层。 还公开了通过冲洗流体在显影期间排出抗蚀剂残留物的方法。

公开(公告)号：US08802360B2

公开(公告)日：2014-08-12

申请号：US13560012

申请日：2012-07-27

申请人： Martin Mazur ,  Henke Dietmar ,  Hans-Juergen Thees

发明人： Martin Mazur ,  Henke Dietmar ,  Hans-Juergen Thees

IPC分类号： G03F7/20

CPC分类号： G03F1/24 ,  G03F1/22 ,  G03F1/50 ,  G03F7/2026 ,  G03F7/2045

摘要： In one example, a reticle disclosed herein includes a body having a center, an arrangement of a plurality of exposure patterns, wherein a center of the arrangement is offset from the center of the body, and at least one open feature defined on or through the body of the reticle. In another example, a method is disclosed that includes forming a layer of photoresist above a plurality of functional die and a plurality of incomplete die, exposing the photoresist material positioned above at least one of the functional die and/or at least one of the incomplete die, performing an incomplete die exposure processes via an open feature of the reticle to expose substantially all of the photoresist material positioned above the plurality of incomplete die, and developing the photoresist to remove the portions of the photoresist material positioned above the incomplete die.

摘要翻译： 在一个示例中，本文公开的掩模版包括具有中心的主体，多个曝光图案的布置，其中该布置的中心偏离主体的中心，以及限定在该主体上或之上的至少一个开放特征 标线的主体。 在另一个实例中，公开了一种方法，其包括在多个功能模具上形成光致抗蚀剂层和多个不完全模具，使位于功能模具中的至少一个上的光致抗蚀剂材料和/或至少一个不完全模具 通过掩模版的开放特征执行不完全的裸片曝光处理，以露出位于多个不完全裸片上方的基本上所有的光致抗蚀剂材料，并且显影光致抗蚀剂以去除位于不完全裸片上方的光刻胶材料的部分。

公开(公告)号：US07981740B2

公开(公告)日：2011-07-19

申请号：US12821583

申请日：2010-06-23

申请人： Markus Lenski ,  Kerstin Ruttloff ,  Martin Mazur ,  Frank Seliger ,  Ralf Otterbach

发明人： Markus Lenski ,  Kerstin Ruttloff ,  Martin Mazur ,  Frank Seliger ,  Ralf Otterbach

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823864 ,  H01L21/823807 ,  H01L29/7843

摘要： When forming transistor elements on the basis of sophisticated high-k metal gate structures, the efficiency of a replacement gate approach may be enhanced by more efficiently adjusting the gate height of transistors of different conductivity type when the dielectric cap layers of transistors may have experienced a different process history and may thus require a subsequent adaptation of the final cap layer thickness in one type of the transistors. For this purpose, a hard mask material may be used during a process sequence for forming offset spacer elements in one gate electrode structure while covering another gate electrode structure.

摘要翻译： 当在复杂的高k金属栅极结构的基础上形成晶体管元件时，可以通过更有效地调节不同导电类型的晶体管的栅极高度来增强置换栅极方法的效率，当晶体管的介质盖层可能经历了 因此可能需要在一种类型的晶体管中随后适应最终的盖层厚度。 为此，可以在用于在一个栅电极结构中形成偏移间隔元件同时覆盖另一栅电极结构的处理顺序期间使用硬掩模材料。

公开(公告)号：US20060223203A1

公开(公告)日：2006-10-05

申请号：US11281997

申请日：2005-11-17

申请人： Uwe Schulze ,  Martin Mazur ,  Andreas Becker

发明人： Uwe Schulze ,  Martin Mazur ,  Andreas Becker

IPC分类号： H01L21/66

CPC分类号： H01L22/20 ,  Y10S430/136

摘要： An advanced process control (APC) architecture comprising a process model that incorporates a target offset term is provided. The APC architecture may be applied to a so-called develop inspect critical dimension (DICD) model using the target offset term to correct at least one exposure parameter on the occurrence of an abrupt event. A corresponding event may, for example, concern a modified reflectivity of processed substrates, for example due to a rework of substrates covered by amorphous carbon material.

公开(公告)号：US06936383B2

公开(公告)日：2005-08-30

申请号：US10306319

申请日：2002-11-27

申请人： Martin Mazur ,  Carsten Hartig ,  Georg Sulzer

发明人： Martin Mazur ,  Carsten Hartig ,  Georg Sulzer

IPC分类号： H01L21/033 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/8234 ,  G03F9/00 ,  H01L21/302

CPC分类号： H01L21/823437 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28123 ,  H01L21/28132 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823481 ,  Y10S438/952 ,  Y10S438/981

摘要： By using conventional spacer and etch techniques, microstructure elements, such as lines and contact openings of integrated circuits, may be formed with dimensions that are mainly determined by the layer thickness of the spacer layer. In a sacrificial layer, an opening is formed by means of standard lithography and etch techniques and, subsequently, a spacer layer is conformally deposited, wherein a thickness of the spacer layer at the sidewalls of the opening substantially determines the effective width of the microstructure element to be formed. By using standard 193 nm lithography and etch processes, gate electrodes of 50 nm and beyond can be obtained without significant changes in standard process recipes.

摘要翻译： 通过使用传统的间隔物和蚀刻技术，可以形成具有主要由间隔层的层厚度确定的尺寸的微结构元件，例如集成电路的线和接触开口。 在牺牲层中，通过标准光刻和蚀刻技术形成开口，随后间隔层被共形沉积，其中间隔层在开口侧壁处的厚度基本上决定了微结构元件的有效宽度 要形成 通过使用标准193nm光刻和蚀刻工艺，可以获得50nm以上的栅电极，而不会在标准工艺配方中显着变化。

公开(公告)号：US20120319205A1

公开(公告)日：2012-12-20

申请号：US13489539

申请日：2012-06-06

申请人： Klaus Hempel ,  Andy Wei ,  Martin Mazur

发明人： Klaus Hempel ,  Andy Wei ,  Martin Mazur

IPC分类号： H01L21/28 ,  H01L27/088

CPC分类号： H01L21/823842

摘要： When forming sophisticated high-k metal gate electrode structures on the basis of a replacement gate approach, the fill conditions upon filling in the highly conductive electrode metal, such as aluminum, may be enhanced by removing an upper portion of the final work function metal, for instance a titanium nitride material in P-channel transistors. In some illustrative embodiments, the selective removal of the metal-containing electrode material in an upper portion of the gate opening may be accomplished without unduly increasing overall process complexity.

摘要翻译： 当在更换栅极方法的基础上形成复杂的高k金属栅电极结构时，填充高导电电极金属（例如铝）时的填充条件可以通过去除最终功函数金属的上部来增强， 例如P沟道晶体管中的氮化钛材料。 在一些说明性实施例中，可以在门开口的上部中选择性地去除含金属的电极材料，而不会过度增加整个工艺的复杂性。

公开(公告)号：US07887978B2

公开(公告)日：2011-02-15

申请号：US12113559

申请日：2008-05-01

申请人： Uwe Griebenow ,  Martin Mazur ,  Wolfram Grundke ,  Andre Poock

发明人： Uwe Griebenow ,  Martin Mazur ,  Wolfram Grundke ,  Andre Poock

IPC分类号： G03F9/00

CPC分类号： G01N21/956 ,  G01N2021/95676 ,  G03F1/84

摘要： Mask defects, such as crystal growth defects and the like, may be efficiently detected and estimated at an early stage of their development by generating test images of the mask under consideration and inspecting the images on the basis of wafer inspection techniques in order to identify repeatedly occurring defects. In some illustrative embodiments, the exposure process for generating the mask images may be performed on the basis of different exposure parameters, such as exposure doses, in order to enhance the probability of detecting defects and also estimating the effect thereof depending on the varying exposure parameters. Consequently, increased reliability may be achieved compared to conventional direct mask inspection techniques.

摘要翻译： 通过产生所考虑的掩模的测试图像并且在晶片检查技术的基础上检查图像以便重复地识别掩模缺陷，例如晶体生长缺陷等，可以在其显影的早期阶段被有效地检测和估计 发生缺陷。 在一些说明性实施例中，用于产生掩模图像的曝光过程可以基于不同的曝光参数（例如曝光剂量）来执行，以增强检测缺陷的可能性，并且还根据变化的曝光参数来估计其效果 。 因此，与传统的直接掩模检查技术相比，可以实现增加的可靠性。

公开(公告)号：US20100330757A1

公开(公告)日：2010-12-30

申请号：US12821583

申请日：2010-06-23

申请人： Markus Lenski ,  Kerstin Ruttloff ,  Martin Mazur ,  Frank Seliger ,  Ralf Otterbach

发明人： Markus Lenski ,  Kerstin Ruttloff ,  Martin Mazur ,  Frank Seliger ,  Ralf Otterbach

IPC分类号： H01L21/8238 ,  H01L21/8234

CPC分类号： H01L21/823864 ,  H01L21/823807 ,  H01L29/7843

摘要： When forming transistor elements on the basis of sophisticated high-k metal gate structures, the efficiency of a replacement gate approach may be enhanced by more efficiently adjusting the gate height of transistors of different conductivity type when the dielectric cap layers of transistors may have experienced a different process history and may thus require a subsequent adaptation of the final cap layer thickness in one type of the transistors. For this purpose, a hard mask material may be used during a process sequence for forming offset spacer elements in one gate electrode structure while covering another gate electrode structure.

摘要翻译： 当在复杂的高k金属栅极结构的基础上形成晶体管元件时，可以通过更有效地调节不同导电类型的晶体管的栅极高度来增强置换栅极方法的效率，当晶体管的介质盖层可能经历了 因此可能需要在一种类型的晶体管中随后适应最终的盖层厚度。 为此，可以在用于在一个栅电极结构中形成偏移间隔元件同时覆盖另一栅电极结构的处理顺序期间使用硬掩模材料。

公开(公告)号：US07314793B2

公开(公告)日：2008-01-01

申请号：US11047129

申请日：2005-01-31

申请人： Kai Frohberg ,  Matthias Schaller ,  Massud Aminpur ,  Martin Mazur ,  Roberto Klingler

发明人： Kai Frohberg ,  Matthias Schaller ,  Massud Aminpur ,  Martin Mazur ,  Roberto Klingler

IPC分类号： H01L21/8238

CPC分类号： H01L29/6653 ,  H01L21/3215 ,  H01L21/32155 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/7843 ,  Y10S438/938

摘要： During the formation of a transistor element, sidewalls spacers are removed or at least partially etched back after ion implantation and silicidation, thereby rendering the mechanical coupling of a contact etch stop layer to the underlying drain and source regions more effective. Hence, the mechanical stress may be substantially induced by the contact etch step layer rather than by a combination of the spacer elements and the etch stop layer, thereby significantly facilitating the stress engineering in the channel region. By additionally performing a plasma treatment, different amounts of stress may be created in different transistor devices without unduly contributing to process complexity.

摘要翻译： 在形成晶体管元件期间，在离子注入和硅化之后去除侧壁间隔物或至少部分地回蚀，从而使接触蚀刻停止层与潜在的漏极和源极区域的机械耦合更有效。 因此，机械应力可以基本上由接触蚀刻步骤层引起，而不是间隔元件和蚀刻停止层的组合，从而显着地促进了沟道区域中的应力工程。 通过额外进行等离子体处理，可以在不同的晶体管器件中产生不同量的应力，而不会不利地导致工艺复杂性。