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公开(公告)号：US09484271B2
公开(公告)日：2016-11-01
申请号：US14686828
申请日：2015-04-15
IPC分类号： H01L21/00 , H01L21/84 , H01L29/78 , H01L21/48 , H01L27/02 , H01L27/12 , H01L21/768 , H01L29/786 , H01L21/74 , H01L21/28 , H01L21/283 , H01L21/311 , H01L29/66
CPC分类号： H01L21/84 , H01L21/28008 , H01L21/283 , H01L21/31111 , H01L21/486 , H01L21/743 , H01L21/76802 , H01L21/76831 , H01L21/76895 , H01L21/76897 , H01L27/0207 , H01L27/1203 , H01L29/66568 , H01L29/78 , H01L29/78648 , H01L29/78654 , H01L2924/0002 , H01L2924/00
摘要： Characteristics of a semiconductor device are improved. A semiconductor device of the present invention includes: (a) a MISFET arranged in an active region formed of a semiconductor region surrounded by an element isolation region; and (b) an insulating layer arranged below the active region. Further, the semiconductor device includes: (c) a p-type semiconductor region arranged below the active region so as to interpose the insulating layer; and (d) an n-type semiconductor region whose conductivity type is opposite to the p-type, arranged below the p-type semiconductor region. And, the p-type semiconductor region includes a connection region extending from below the insulating layer, and the p-type semiconductor region and a gate electrode of the MISFET are connected to each other by a shared plug which is an integrally-formed conductive film extending from above the gate electrode to above the connection region.
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公开(公告)号：US09343527B2
公开(公告)日：2016-05-17
申请号：US13691800
申请日：2012-12-02
发明人： Jiro Yugami , Toshiaki Iwamatsu , Katsuyuki Horita , Hideki Makiyama , Yasuo Inoue , Yoshiki Yamamoto
IPC分类号： H01L29/76 , H01L21/02 , H01L21/70 , H01L29/06 , H01L21/762 , H01L21/8238 , H01L27/12
CPC分类号： H01L21/76283 , H01L21/02164 , H01L21/0217 , H01L21/30604 , H01L21/31053 , H01L21/31111 , H01L21/76224 , H01L21/76229 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L27/1207 , H01L29/0649
摘要： A first MISFET which is a semiconductor element is formed on an SOI substrate. The SOI substrate includes a supporting substrate which is a base, BOX layer which is an insulating layer formed on a main surface (surface) of the supporting substrate, that is, a buried oxide film; and an SOI layer which is a semiconductor layer formed on the BOX layer. The first MISFET as a semiconductor element is formed to the SOI layer. In an isolation region, an isolation groove is formed penetrating though the SOI layer and the BOX layer so that a bottom surface of the groove is positioned in the middle of a thickness of the supporting substrate. An isolation film is buried in the isolation groove being formed. Then, an oxidation resistant film is interposed between the BOX layer and the isolation film.
摘要翻译： 在SOI衬底上形成作为半导体元件的第一MISFET。 SOI衬底包括作为基底的支撑衬底，BOX层，其是形成在支撑衬底的主表面（表面）上的绝缘层，即掩埋氧化物膜; 以及作为在BOX层上形成的半导体层的SOI层。 作为半导体元件的第一MISFET形成于SOI层。 在隔离区域中，穿过SOI层和BOX层形成隔离槽，使得槽的底面位于支撑基板的厚度的中间。 隔离膜被埋在正在形成的隔离槽中。 然后，在BOX层和隔离膜之间插入抗氧化膜。
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公开(公告)号：US20160056264A1
公开(公告)日：2016-02-25
申请号：US14929646
申请日：2015-11-02
CPC分类号： H01L29/1083 , H01L21/265 , H01L21/74 , H01L21/76897 , H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/0847 , H01L29/0878 , H01L29/41783 , H01L29/4238 , H01L29/66477 , H01L29/665 , H01L29/66537 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66742 , H01L29/66757 , H01L29/66772 , H01L29/7824 , H01L29/7833 , H01L29/78606 , H01L29/78621 , H01L29/78651 , H01L29/78654
摘要： Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.
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公开(公告)号：US20150325673A1
公开(公告)日：2015-11-12
申请号：US14803040
申请日：2015-07-18
IPC分类号： H01L29/66 , H01L21/266 , H01L29/417
CPC分类号： H01L29/7827 , H01L21/266 , H01L29/41783 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66628 , H01L29/66666 , H01L29/66772 , H01L29/78621
摘要： A semiconductor device is manufactured by using an SOI substrate having an insulating layer on a substrate and a semiconductor layer on the insulating layer. The semiconductor device is provided with a gate electrode formed on the semiconductor layer via a gate insulating film, a sidewall spacer formed on a sidewall of the gate electrode, a semiconductor layer for source/drain that is epitaxially grown on the semiconductor layer, and a sidewall spacer formed on a sidewall of the semiconductor layer.
摘要翻译： 通过使用在衬底上具有绝缘层的SOI衬底和绝缘层上的半导体层来制造半导体器件。 半导体器件设置有通过栅极绝缘膜形成在半导体层上的栅极电极，形成在栅电极的侧壁上的侧壁间隔物，在半导体层上外延生长的用于源极/漏极的半导体层，以及 侧壁间隔物形成在半导体层的侧壁上。
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公开(公告)号：US09130039B2
公开(公告)日：2015-09-08
申请号：US13962066
申请日：2013-08-08
IPC分类号： H01L29/76 , H01L29/78 , H01L29/66 , H01L29/417 , H01L29/786
CPC分类号： H01L29/7827 , H01L21/266 , H01L29/41783 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66628 , H01L29/66666 , H01L29/66772 , H01L29/78621
摘要： A semiconductor device is manufactured by using an SOI substrate having an insulating layer on a substrate and a semiconductor layer on the insulating layer. The semiconductor device is provided with a gate electrode formed on the semiconductor layer via a gate insulating film, a sidewall spacer formed on a sidewall of the gate electrode, a semiconductor layer for source/drain that is epitaxially grown on the semiconductor layer, and a sidewall spacer formed on a sidewall of the semiconductor layer.
摘要翻译： 通过使用在衬底上具有绝缘层的SOI衬底和绝缘层上的半导体层来制造半导体器件。 半导体器件设置有通过栅极绝缘膜形成在半导体层上的栅电极，形成在栅电极的侧壁上的侧壁间隔物，在半导体层上外延生长的用于源极/漏极的半导体层，以及 侧壁间隔物形成在半导体层的侧壁上。
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公开(公告)号：US20150140768A1
公开(公告)日：2015-05-21
申请号：US14469371
申请日：2014-08-26
发明人： Yoshiki Yamamoto
CPC分类号： H01L29/66575 , H01L29/66477 , H01L29/6653 , H01L29/6656 , H01L29/66628 , H01L29/7834
摘要： A performance of a semiconductor device is improved. A gate electrode is formed on an SOI substrate via a gate insulating film, and a laminated film including an insulating film IL2 and an insulating film IL3 on the insulating film IL2 is formed on the SOI substrate so as to cover the gate electrode, and then, a sidewall spacer formed of the laminated film is formed on a side wall of the gate electrode by etching back the laminated film. Then, a semiconductor layer is epitaxially grown on a semiconductor layer of the SOI substrate SUB which is not covered with the gate electrode and the sidewall spacer but is exposed, and then, an oxide film is formed on a surface of the semiconductor layer by oxidizing the surface of the semiconductor layer. Then, the insulating film IL3 forming the sidewall spacer is removed.
摘要翻译： 提高了半导体器件的性能。 通过栅极绝缘膜在SOI衬底上形成栅电极，在SOI衬底上形成包括绝缘膜IL2上的绝缘膜IL2和绝缘膜IL3的层叠膜，以覆盖栅电极，然后 通过对层压膜进行回蚀而在栅电极的侧壁上形成由叠层膜形成的侧壁间隔物。 然后，在SOI衬底SUB的半导体层上外延生长半导体层，SOI衬底SUB未被栅电极和侧壁间隔物覆盖但被暴露，然后通过氧化形成在半导体层的表面上的氧化膜 半导体层的表面。 然后，去除形成侧壁间隔物的绝缘膜IL3。
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公开(公告)号：US20140353756A1
公开(公告)日：2014-12-04
申请号：US14291095
申请日：2014-05-30
发明人： Yoshiki Yamamoto
IPC分类号： H01L27/12 , H01L29/06 , H01L21/8234
CPC分类号： H01L27/1203 , H01L21/76283 , H01L21/84 , H01L27/1104 , H01L27/1116 , H01L29/78
摘要： A semiconductor device using an SOI (Silicon On Insulator) substrate, capable of preventing malfunction of MISFETs (Metal Insulator Semiconductor Field Effect Transistor) and thus improving the reliability of the semiconductor device. Moreover, the parasitic resistance of the MISFETs is reduced, and the performance of the semiconductor device is improved. An epitaxial layer formed on an SOI layer above an SOI substrate is formed to have a large width so as to cover the ends of the upper surface of an isolation region adjacent to the SOI layer. By virtue of this, contact plugs of which formation positions are misaligned are prevented from being connected to a semiconductor substrate below the SOI layer. Moreover, by forming the epitaxial layer at a large width, the ends of the SOI layer therebelow are prevented from being silicided. As a result, increase in the parasitic resistance of MISFETs is prevented.
摘要翻译： 使用SOI（绝缘体上硅）衬底的半导体器件，能够防止MISFET（金属绝缘体半导体场效应晶体管）的故障，从而提高半导体器件的可靠性。 此外，MISFET的寄生电阻降低，并且提高了半导体器件的性能。 形成在SOI衬底上的SOI层上的外延层形成为具有大的宽度，以覆盖与SOI层相邻的隔离区的上表面的端部。 由此，防止形成位置不对准的接触插塞连接到SOI层下面的半导体衬底。 此外，通过以大的宽度形成外延层，防止其下方的SOI层的端部被硅化。 结果，防止了MISFET的寄生电阻的增加。
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公开(公告)号：US11996448B2
公开(公告)日：2024-05-28
申请号：US18135426
申请日：2023-04-17
IPC分类号： H01L21/82 , H01L21/265 , H01L21/74 , H01L21/768 , H01L21/8234 , H01L21/8238 , H01L21/84 , H01L27/12 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/78 , H01L29/786
CPC分类号： H01L29/1083 , H01L21/265 , H01L21/74 , H01L21/76897 , H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/0847 , H01L29/0878 , H01L29/41783 , H01L29/4238 , H01L29/66477 , H01L29/665 , H01L29/6653 , H01L29/66537 , H01L29/66545 , H01L29/66553 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66742 , H01L29/66757 , H01L29/66772 , H01L29/6681 , H01L29/7824 , H01L29/7833 , H01L29/78606 , H01L29/78621 , H01L29/78651 , H01L29/78654
摘要： Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.
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公开(公告)号：US11695012B2
公开(公告)日：2023-07-04
申请号：US16928542
申请日：2020-07-14
IPC分类号： H01L27/12 , H01L29/66 , H01L29/78 , H01L21/8234 , H01L29/417 , H01L21/8238
CPC分类号： H01L27/1203 , H01L27/1207 , H01L29/66477 , H01L29/66628 , H01L29/66651 , H01L29/7834 , H01L21/823418 , H01L21/823814 , H01L29/41783
摘要： On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.
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公开(公告)号：US10115452B2
公开(公告)日：2018-10-30
申请号：US15620406
申请日：2017-06-12
发明人： Yoshiki Yamamoto
IPC分类号： G11C11/4074 , G11C11/417 , G05F3/20 , H01L21/8238 , H01L27/02 , G11C5/14 , H01L27/11 , H01L27/12
摘要： A semiconductor device includes a substrate, a circuit having a transistor formed on the substrate, an oscillation circuit generating a frequency signal, a substrate voltage generation circuit generating a substrate voltage in accordance with the frequency signal from the oscillation circuit, and a control circuit varying a frequency of the frequency signal from the oscillation circuit during a stand-by period of the circuit.
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