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    Thin film transistor having an improved gate structure and gate coverage by the gate dielectric
    11.
    发明授权
    Thin film transistor having an improved gate structure and gate coverage by the gate dielectric 失效
    具有改进的门电极结构和栅极覆盖的薄膜晶体管

    公开(公告)号：US5132745A

    公开(公告)日：1992-07-21

    申请号：US758474

    申请日：1991-09-06

    申请人： Robert F. Kwasnick ,  Ching-Yeu Wei

    发明人： Robert F. Kwasnick ,  Ching-Yeu Wei

    IPC分类号： H01L29/40 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

    CPC分类号： H01L29/66765 ,  H01L21/28008 ,  H01L29/42384 ,  H01L29/4908

    摘要： A thin film transistor includes a two-layer gate metallization comprising a relatively thin first layer of a first conductor and a relatively thick second layer of a second conductor with the second conductor being capable of being etched with an etchant that produces substantially no etching of the first conductor layer. During device fabrication, the thick gate metallization layer (second conductor) is selectively etched until all of that material is removed in the openings in the mask. The thin lower layer (first conductor) is then etched with a minimum of etching into the substrate. The gate dielectric and subsequent layers deposited over this gate metallization have high integrity and highly reliable continuity because of the sloped nature of the gate metallization sidewalls, and because of the shallow gate metallization topography due to minimization of substrate etching during gate metallization patterning.

    摘要翻译： 薄膜晶体管包括双层栅极金属化，其包括相对薄的第一导体的第一层和相对较厚的第二导体的第二层，其中第二导体能够用蚀刻剂进行蚀刻，所述蚀刻剂基本上不产生蚀刻 第一导体层。 在器件制造期间，选择性地蚀刻厚栅极金属化层（第二导体），直到在掩模的开口中去除所有这些材料。 然后将薄的下层（第一导体）用最少的蚀刻蚀刻到衬底中。 沉积在该栅极金属化之上的栅极电介质层和随后的层具有高完整性和高度可靠的连续性，因为栅极金属化侧壁具有倾斜的性质，并且由于在栅极金属化图案化期间由于最小化衬底蚀刻而导致浅栅极金属化形貌。

    Device self-alignment by propagation of a reference structure's topography
    12.
    发明授权
    Device self-alignment by propagation of a reference structure's topography 失效
    通过参考结构的地形的传播进行设备自对准

    公开(公告)号：US5340758A

    公开(公告)日：1994-08-23

    申请号：US938562

    申请日：1992-08-28

    申请人： Ching-Yeu Wei ,  George E. Possin ,  Robert F. Kwasnick

    发明人： Ching-Yeu Wei ,  George E. Possin ,  Robert F. Kwasnick

    IPC分类号： H01L29/40 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

    CPC分类号： H01L29/66765 ,  H01L21/28008 ,  H01L29/42384 ,  H01L29/78669

    摘要： A self-aligned, inverted, thin film field effect transistor is produced by patterning the gate electrode to have tapered edges followed by conformal deposition of subsequent layers of the device structure up through a support layer followed by deposition of a subordinate layer such as the source/drain metallization) on the support layer. The subordinate layer itself may be a planarization or non-conformal layer or may have a subsequent non-conformal planarization layer disposed thereon. Thereafter, the structure is non-selectively etched (preferably reactive ion etched) until the support layer is exposed by the creation of an aperture in the subordinate layer in alignment with raised portions of the reference layer while leaving the subordinate layer present on other parts of the structure. Thereafter, the remainder of the device is fabricated with the source and drain electrodes self-aligned with respect to the gate conductor using a selective etch method.

    摘要翻译： 通过对栅电极进行图案化以产生渐缩边缘，随后将器件结构的后续层向上保持沉积通过支撑层，随后沉积下层（例如源极）而产生自对准反转的薄膜场效应晶体管 /漏极金属化）。 下层本身可以是平面化或非保形层，或者可以具有设置在其上的随后的非保形平面化层。 此后，结构被非选择性蚀刻（优选为反应离子蚀刻），直到支撑层通过在下位层中形成与参考层的凸起部分对准的孔而暴露，同时使下层存在于其它部分 结构。 此后，使用选择性蚀刻方法，使源极和漏极相对于栅极导体自对准制造器件的其余部分。

    X-ray collimator
    13.
    发明授权
    X-ray collimator 失效
    X射线准直仪

    公开(公告)号：US5293417A

    公开(公告)日：1994-03-08

    申请号：US30909

    申请日：1993-03-15

    申请人： Ching-Yeu Wei ,  Robert F. Kwasnick ,  George E. Possin

    发明人： Ching-Yeu Wei ,  Robert F. Kwasnick ,  George E. Possin

    IPC分类号： G21K1/02

    CPC分类号： G21K1/025

    摘要： A collimator for use in an imaging system with a radiation point source is formed from a plurality of collimator plates stacked together. Passages in each collimator plate in conjunction with the respective passages in adjoining plates form a plurality of channels through the collimator. The channel longitudinal axes are aligned with selected orientation angles that correspond to the direct beam path from the radiation source to the radiation detectors. The collimator plates are made up of patterned sheets of radiation absorbent material or alternatively comprise patterned photosensitive material substrates coated with a radiation absorbent material. The cross-sectional shape of each channel corresponds to the cross-sectional shape of the radiation detecting area of the detector element adjoining the channel. A method of forming a collimator includes the steps of selectively removing material from the collimator plates to form the passages therein, and stacking the patterned collimator plates together to align them so that the respective adjacent passages form a channel aligned with respective selected orientation angles corresponding to direct paths of radiation from the radiation source to the detector elements in the assembled array.

    摘要翻译： 用于具有辐射点源的成像系统中的准直器由堆叠在一起的多个准直器板形成。 每个准直板中的通道与相邻板中的相应通道结合形成通过准直器的多个通道。 通道纵向轴线对应于对应于从辐射源到辐射探测器的直接光束路径的选定取向角度。 准直板由图案化的辐射吸收材料片构成，或者包括涂覆有辐射吸收材料的图案化感光材料基底。 每个通道的横截面形状对应于邻近通道的检测器元件的辐射检测区域的横截面形状。 一种形成准直器的方法包括以下步骤：选择性地从准直板移除材料以在其中形成通道，并且将图案化的准直器板堆叠在一起以对准它们，使得相应的相邻通道形成与各自选定的取向角对应的通道 从辐射源到组装阵列中的检测器元件的直接辐射路径。

    Method of fabricating radiation imager with single passivation dielectric for transistor and diode
    14.
    发明授权
    Method of fabricating radiation imager with single passivation dielectric for transistor and diode 失效
    用于晶体管和二极管制造单个钝化电介质的辐射成像仪的方法

    公开(公告)号：US5516712A

    公开(公告)日：1996-05-14

    申请号：US330955

    申请日：1994-10-28

    申请人： Ching-Yeu Wei ,  Robert F. Kwasnick ,  Brian W. Giambattista

    发明人： Ching-Yeu Wei ,  Robert F. Kwasnick ,  Brian W. Giambattista

    IPC分类号： H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L27/146 ,  H01L27/15 ,  H01L29/786 ,  H01L31/10

    CPC分类号： H01L27/14643 ,  H01L27/1214

    摘要： A radiation imager includes a photosensor array having a plurality of individually addressable pixels, each pixel having a photosensor island and an associated thin film transistor (TFT) disposed to selectively electrically couple the photosensor island to a predetermined address line. In each pixel a single common passivation layer is disposed over the TFT and the photosensor island such that the passivation layer is adjacent to both the outer surfaces of the TFT and portions of the photosensor island. In a method of fabricating a photosensor array as described above, after depositon of a source-drain metal layer, the layer is left unpatterned until after the photosensor island has been formed. In the formation of the photosensor island the source-drain metal layer serves as an etch stop to protect the TFT. Following formation of the photosensor island, the source-drain metal layer is patterned to form source and drain electrodes and fabrication of the TFT is completed. The single common passivation layer is then deposited over both the TFT and the photosensor island.

    摘要翻译： 辐射成像仪包括具有多个可独立寻址的像素的光电传感器阵列，每个像素具有光电传感器岛和相关联的薄膜晶体管（TFT），用于选择性地将光电传感器岛电耦合到预定的地址线。 在每个像素中，单个公共钝化层设置在TFT和光电传感器岛上，使得钝化层与TFT的外表面和光电传感器岛的两个部分相邻。 在如上所述的制造光电传感器阵列的方法中，在源极 - 漏极金属层沉积之后，该层被保持未图案化，直到形成光电传感器岛为止。 在光电传感器岛的形成中，源极 - 漏极金属层用作蚀刻停止以保护TFT。 在形成光电传感器岛之后，对源极 -​​ 漏极金属层进行图案化以形成源极和漏极并完成TFT的制造。 然后将单个公共钝化层沉积在TFT和光电传感器岛上。

    Repair line structure for thin film electronic devices
    15.
    发明授权
    Repair line structure for thin film electronic devices 失效
    维修薄膜电子设备的线路结构

    公开(公告)号：US5475246A

    公开(公告)日：1995-12-12

    申请号：US169290

    申请日：1993-12-20

    申请人： Ching-Yeu Wei ,  Roger S. Salisbury ,  Robert F. Kwasnick

    发明人： Ching-Yeu Wei ,  Roger S. Salisbury ,  Robert F. Kwasnick

    IPC分类号： G02F1/1362 ,  H01L21/768 ,  H01L21/82 ,  H01L23/522 ,  H01L23/525 ,  H01L27/146 ,  H01L27/10 ,  H01L27/15

    CPC分类号： H01L27/146 ,  H01L21/76892 ,  H01L23/525 ,  G02F2001/136263 ,  H01L2924/0002

    摘要： Repair lines in an imager device include protective layers disposed over steps in the repair lines where the repair lines extend over underlying components in the imager array. The protective layers each include a layer of polyimide to provide protection for the step portions of the conductive repair line from etchants and the like to which the conductive line is exposed during fabrication processes for the imager array. The protective layers are disposed over the steps of a conductive line in a repair crossover region so as to provide a repair area free from the protective material of the protective layers disposed thereon in the repair crossover region where the conductive repair line is disposed in vertical alignment with an underlying address line.

    摘要翻译： 成像设备中的修复线包括设置在修复线上的步骤之上的保护层，其中修复线延伸到成像器阵列中的下面的部件上。 保护层各自包括聚酰亚胺层，以便在成像器阵列的制造过程期间为导电线暴露的蚀刻剂等提供对导电修补线的台阶部分的保护。 保护层设置在修复交叉区域中的导电线的台阶上，以便提供修复区域，该修复区域不设置在修复交叉区域中的保护层的保护材料，其中导电修复线设置成垂直对准 与底层地址行。

    Solid state radiation imager with high integrity barrier layer and method of fabricating
    16.
    发明授权
    Solid state radiation imager with high integrity barrier layer and method of fabricating 失效
    具有高完整性阻挡层的固态辐射成像仪

    公开(公告)号：US5463225A

    公开(公告)日：1995-10-31

    申请号：US99370

    申请日：1993-07-29

    申请人： Robert F. Kwasnick ,  Ching-Yeu Wei ,  Jack D. Kingsley

    发明人： Robert F. Kwasnick ,  Ching-Yeu Wei ,  Jack D. Kingsley

    IPC分类号： G01J1/02 ,  G01T1/20 ,  H01L27/146 ,  H01L31/0216 ,  H01L31/0232 ,  H01L31/105 ,  H01L31/055

    CPC分类号： H01L31/0216 ,  H01L31/02322 ,  H01L31/1055

    摘要： A radiation imager includes a photosensor barrier layer disposed between an amorphous silicon photosensor array and the scintillator. The barrier layer includes two strata, the first stratum being silicon oxide disposed over the upper conductive layer of the photosensor array and the second stratum is silicon nitride that is disposed over the first stratum. The photosensor barrier layer has a shape that substantially conforms to the the shape of the underlying upper conductive layer and has a maximum thickness of about 3 microns. The silicon oxide and silicon nitride are deposited in a vapor deposition process at less than about 250.degree. C. using tetraethoxysilane (TEOS) as the silicon source gas.

    摘要翻译： 辐射成像仪包括设置在非晶硅光电传感器阵列和闪烁体之间的光电传感器阻挡层。 阻挡层包括两层，第一层是设置在光传感器阵列的上导电层上的氧化硅，第二层是设置在第一层上的氮化硅。 光电传感器阻挡层具有基本上符合下面的上导电层的形状并具有约3微米的最大厚度的形状。 使用四乙氧基硅烷（TEOS）作为硅源气体，在小于约250℃的气相沉积工艺中沉积氧化硅和氮化硅。

    Positive control of the source/drain-gate overlap in self-aligned TFTS via a top hat gate electrode configuration
    17.
    发明授权
    Positive control of the source/drain-gate overlap in self-aligned TFTS via a top hat gate electrode configuration 失效
    通过顶帽栅极电极配置对自对准TFTS中的源极/漏极 - 栅极重叠进行正向控制

    公开(公告)号：US5156986A

    公开(公告)日：1992-10-20

    申请号：US667149

    申请日：1991-03-11

    申请人： Ching-Yeu Wei ,  George E. Possin ,  Robert F. Kwasnick

    发明人： Ching-Yeu Wei ,  George E. Possin ,  Robert F. Kwasnick

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49

    CPC分类号： H01L29/66765 ,  H01L21/28008 ,  H01L29/42384 ,  H01L29/4908

    摘要： Positive control over the length of the overlap between the gate electrode and the source and drain electrodes in a thin film transistor is provided by a gate conductor layer comprising two different conductors having differing etching characteristics. As part of the gate conductor pattern definition process, both gate conductors are etched to expose the underlying material and the upper gate conductor layer is etched back to expose the first gate conductor layer in accordance with the desired overlap between the gate electrode and the source and drain electrodes. Thereafter, the remainder of the device is fabricated with the source and drain electrodes self-aligned with respect to the second gate conductor layer using a planarization and non-selective etch method.

    摘要翻译： 通过包括具有不同蚀刻特性的两个不同导体的栅极导体层来提供薄膜晶体管中的栅极电极和源极和漏极之间的重叠长度的正向控制。 作为栅极导体图案定义过程的一部分，蚀刻两个栅极导体以暴露下面的材料，并且根据栅电极和源之间的期望重叠，蚀刻回去上栅极导体层以暴露第一栅极导体层，以及 漏电极。 此后，使用平面化和非选择性蚀刻方法，用相对于第二栅极导体层自对准的源极和漏极制造器件的其余部分。

    Storage capacitor design for a solid state imager
    20.
    发明授权
    Storage capacitor design for a solid state imager 有权
    存储电容设计为固态成像仪

    公开(公告)号：US07145152B2

    公开(公告)日：2006-12-05

    申请号：US10687407

    申请日：2003-10-14

    申请人： Ji-Ung Lee ,  Douglas Albagli ,  George Edward Possin ,  William Andrew Hennessy ,  Ching-Yeu Wei

    发明人： Ji-Ung Lee ,  Douglas Albagli ,  George Edward Possin ,  William Andrew Hennessy ,  Ching-Yeu Wei

    IPC分类号： G02F1/136 ,  H01L31/115 ,  G06T11/00

    CPC分类号： H01L27/14658

    摘要： Storage capacitor design for a solid state imager. The imager includes several pixels disposed on a substrate in an imaging array pattern. Each pixel includes a photosensor coupled to a thin film switching transistor. Several scan lines are disposed at a first level with respect to the substrate along a first axis and several data lines are disposed at a second level along a second axis of the imaging array. Several data lines disposed at a second level with respect to the substrate along a second axis of the imaging array pattern. Each pixel comprises a storage capacitor coupled parallel to the photosensor, the storage capacitor comprising a storage capacitor electrode and a capacitor common electrode.

    摘要翻译： 存储电容设计为固态成像仪。 成像器包括以成像阵列图案设置在基板上的若干像素。 每个像素包括耦合到薄膜开关晶体管的光电传感器。 若干扫描线沿着第一轴相对于基板设置在第一水平面上，并且沿着成像阵列的第二轴将多条数据线布置在第二级。 沿着成像阵列图案的第二轴相对于衬底设置在第二水平的几条数据线。 每个像素包括与光电传感器并联耦合的存储电容器，存储电容器包括存储电容器电极和电容器公共电极。