公开(公告)号：US08217463B2

公开(公告)日：2012-07-10

申请号：US13021403

申请日：2011-02-04

Applicant: Rohit Pal ,  Michael Hargrove ,  Frank Bin Yang

Inventor： Rohit Pal ,  Michael Hargrove ,  Frank Bin Yang

IPC: H01L29/66

CPC classification number: H01L29/66651 ,  H01L21/28123 ,  H01L21/28194 ,  H01L21/28247 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

Abstract: Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. Methods for fabricating a semiconductor device include providing a semiconductor substrate having an active region and a shallow trench isolation (STI) region. Epitaxial layer is formed on the active region to define a lateral overhang portion in a divot at the active region/STI region interface. A gate stack is formed having a first gate stack-forming layer overlying the semiconductor substrate. First gate stack-forming layer includes a non-conformal layer of metal gate-forming material which is directionally deposited to form a thinned break portion just below the lateral overhang portion. After the step of forming the gate stack, a first portion of the non-conformal layer is in the gate stack and a second portion is exposed. The thinned break portion at least partially isolates the first and second portions during subsequent etch chemistries.

Abstract translation: 提供了在由这些方法制造的半导体器件和半导体器件的制造期间保护栅极堆叠的方法。 制造半导体器件的方法包括提供具有有源区和浅沟槽隔离（STI）区的半导体衬底。 在有源区上形成外延层，以在有源区/ STI区界面上的边界中限定一个横向伸出部分。 形成具有覆盖在半导体衬底上的第一栅叠层形成层的栅叠层。 第一栅极堆叠形成层包括定向沉积以形成刚好在横向突出部分下方的变薄的断裂部分的非保形层的金属栅极形成材料。 在形成栅极堆叠的步骤之后，非共形层的第一部分在栅极堆叠中并且第二部分被暴露。 减薄断裂部分在随后的蚀刻化学过程中至少部分地隔离第一和第二部分。

公开(公告)号：US07670934B1

公开(公告)日：2010-03-02

申请号：US12359764

申请日：2009-01-26

Applicant: Rohit Pal ,  Frank Bin Yang

Inventor： Rohit Pal ,  Frank Bin Yang

IPC: H01L21/20 ,  H01L21/36

CPC classification number: H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84

Abstract: Methods of fabricating a semiconductor device on and in a semiconductor substrate having a first region and a second region are provided. In accordance with an exemplary embodiment of the invention, a method comprises forming a first gate stack overlying the first region and a second gate stack overlying the second region, etching into the substrate first recesses and second recesses, the first recesses aligned at least to the first gate stack in the first region, and the second recesses aligned at least to the second gate stack in the second region, epitaxially growing a first stress-inducing monocrystalline material in the first and second recesses, removing the first stress-inducing monocrystalline material from the first recesses, and epitaxially growing a second stress-inducing monocrystalline material in the first recesses, wherein the second stress-inducing monocrystalline material has a composition different from the first stress-inducing monocrystalline material.

Abstract translation: 提供了在具有第一区域和第二区域的半导体衬底上和半导体衬底中制造半导体器件的方法。 根据本发明的示例性实施例，一种方法包括形成覆盖第一区域的第一栅极堆叠和覆盖第二区域的第二栅极堆叠，蚀刻到衬底中的第一凹陷和第二凹槽，第一凹陷至少对准 第一栅极堆叠在第一区域中，并且第二凹陷至少对准第二区域中的第二栅极堆叠，在第一和第二凹槽中外延生长第一应力诱导单晶材料，从第一和第二凹槽中去除第一应力诱导单晶材料 第一凹陷，并且在第一凹陷中外延生长第二应力诱导单晶材料，其中第二应力诱导单晶材料具有不同于第一应力诱导单晶材料的组成。

公开(公告)号：US20080119031A1

公开(公告)日：2008-05-22

申请号：US11562209

申请日：2006-11-21

Applicant: Rohit Pal ,  Igor Peidous ,  David Brown

Inventor： Rohit Pal ,  Igor Peidous ,  David Brown

IPC: H01L21/20 ,  H01L21/36 ,  H01L31/20

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/045 ,  H01L29/165 ,  H01L29/66636

Abstract: A stress enhanced MOS transistor and methods for its fabrication are provided. In one embodiment the method comprises forming a gate electrode overlying and defining a channel region in a monocrystalline semiconductor substrate. A trench having a side surface facing the channel region is etched into the monocrystalline semiconductor substrate adjacent the channel region. The trench is filled with a second monocrystalline semiconductor material having a first concentration of a substitutional atom and with a third monocrystalline semiconductor material having a second concentration of the substitutional atom. The second monocrystalline semiconductor material is epitaxially grown to have a wall thickness along the side surface sufficient to exert a greater stress on the channel region than the stress that would be exerted by a monocrystalline semiconductor material having the second concentration if the trench was filled by the third monocrystalline material alone.

Abstract translation: 提供了一种应力增强型MOS晶体管及其制造方法。 在一个实施例中，该方法包括形成覆盖并限定单晶半导体衬底中的沟道区的栅电极。 具有面向通道区域的侧表面的沟槽被蚀刻到与沟道区域相邻的单晶半导体衬底中。 沟槽填充有具有第一浓度的取代原子的第二单晶半导体材料和具有第二浓度取代原子的第三单晶半导体材料。 第二单晶半导体材料被外延生长以具有沿着侧表面的壁厚，足以在沟道区域施加比由具有第二浓度的单晶半导体材料施加的应力更大的应力，如果沟槽由 第三单晶材料。

公开(公告)号：US07195036B2

公开(公告)日：2007-03-27

申请号：US10696889

申请日：2003-10-30

Applicant: Mark A. Burns ,  Rohit Pal

Inventor： Mark A. Burns ,  Rohit Pal

IPC: F15C1/04 ,  F16K13/10

CPC classification number: F16K99/0017 ,  B01F13/0059 ,  B01J19/0093 ,  B01J2219/00783 ,  B01J2219/00788 ,  B01J2219/00828 ,  B01J2219/00873 ,  B01J2219/00889 ,  B01J2219/00891 ,  B01L3/502707 ,  B01L3/502738 ,  B01L3/502784 ,  B01L2200/12 ,  B01L2400/0487 ,  B01L2400/0677 ,  F16K99/0001 ,  F16K99/0015 ,  F16K99/0019 ,  F16K99/0036 ,  F16K99/0044 ,  F16K2099/0074 ,  F16K2099/0076 ,  F16K2099/0084 ,  Y10T137/2196 ,  Y10T137/4643

Abstract: The movement and mixing of microdroplets through microchannels is described employing silicon-based microscale devices, comprising microdroplet transport channels, reaction regions, electrophoresis modules, and radiation detectors. The discrete droplets are differentially heated and propelled through etched channels. Electronic components are fabricated on the same substrate material, allowing sensors and controlling circuitry to be incorporated in the same device.

Abstract translation: 使用硅微量元件描述了通过微通道的微滴的运动和混合，包括微滴输送通道，反应区域，电泳模块和辐射探测器。 离散的液滴通过蚀刻通道进行差分加热和推进。 电子元件制造在相同的基板材料上，允许将传感器和控制电路并入同一设备。

公开(公告)号：US08673710B2

公开(公告)日：2014-03-18

申请号：US13197387

申请日：2011-08-03

Applicant: Stephan Kronholz ,  Rohit Pal

Inventor： Stephan Kronholz ,  Rohit Pal

IPC: H01L21/8238

CPC classification number: H01L21/823878 ,  H01L21/823807 ,  H01L21/823814

Abstract: When forming sophisticated high-k metal gate electrode structures, the uniformity of the device characteristics may be enhanced by growing a threshold adjusting semiconductor alloy on the basis of a hard mask regime, which may result in a less pronounced surface topography, in particular in densely packed device areas. To this end, in some illustrative embodiments, a deposited hard mask material may be used for selectively providing an oxide mask of reduced thickness and superior uniformity.

Abstract translation: 当形成复杂的高k金属栅电极结构时，可以通过基于硬掩模方式生长阈值调节半导体合金来增强器件特性的均匀性，这可能导致不太显着的表面形貌，特别是在密集 包装设备区域。 为此，在一些说明性实施例中，沉积的硬掩模材料可用于选择性地提供厚度减小和均匀性优异的氧化物掩模。

公开(公告)号：US08551599B2

公开(公告)日：2013-10-08

申请号：US12551071

申请日：2009-08-31

Applicant: Zhishan Hua ,  Erdogan Gulari ,  Mark A. Burns ,  Rohit Pal ,  Onnop Srivannavit

Inventor： Zhishan Hua ,  Erdogan Gulari ,  Mark A. Burns ,  Rohit Pal ,  Onnop Srivannavit

IPC: B32B3/24 ,  B32B3/26 ,  F16K7/12 ,  F16K7/17 ,  F16K31/02 ,  F16K31/126 ,  B81C1/00

CPC classification number: F16K99/0032 ,  B01L3/502707 ,  B01L3/502715 ,  B01L3/50273 ,  B01L3/502738 ,  B01L3/502746 ,  B01L2300/0819 ,  B01L2400/0481 ,  B01L2400/0655 ,  B01L2400/0677 ,  F15B15/10 ,  F16K99/0044 ,  Y10T137/0391 ,  Y10T137/1624 ,  Y10T137/1812 ,  Y10T137/2142 ,  Y10T137/218 ,  Y10T137/2191 ,  Y10T137/2196 ,  Y10T137/2202 ,  Y10T137/2218 ,  Y10T428/23 ,  Y10T428/234 ,  Y10T428/24322 ,  Y10T428/24331 ,  Y10T428/24612

Abstract: A microactuator may be configured by activating a source of electromagnetic radiation to heat and melt a selected set of phase-change plugs embedded in a substrate of the microactuator, pressurizing a common pressure chamber adjacent to each of the plugs to deform the melted plugs, and deactivating the source of electromagnetic radiation to cool and solidify the melted plugs.

公开(公告)号：US20130115773A1

公开(公告)日：2013-05-09

申请号：US13289122

申请日：2011-11-04

Applicant: Rohit Pal ,  Rolf Stephan ,  Andreas Ott

Inventor： Rohit Pal ,  Rolf Stephan ,  Andreas Ott

IPC: H01L21/311

CPC classification number: H01L21/3105 ,  H01L21/31155 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/84 ,  H01L29/66545 ,  H01L29/7833

Abstract: When forming sophisticated high-k metal gate electrode structures on the basis of a replacement gate approach, pronounced loss of the interlayer dielectric material may be avoided by inserting at least one surface modification process, for instance in the form of a nitridation process. In this manner, leakage paths caused by metal residues formed in the interlayer dielectric material may be significantly reduced.

Abstract translation: 当基于替代栅极方法形成复杂的高k金属栅电极结构时，可以通过插入至少一个表面改性工艺（例如以氮化工艺的形式）来避免层间绝缘材料的显着损失。 以这种方式，可以显着地减少由层间电介质材料中形成的金属残留物引起的泄漏路径。

公开(公告)号：US08293609B2

公开(公告)日：2012-10-23

申请号：US13355221

申请日：2012-01-20

Applicant: Rohit Pal ,  Frank Bin Yang ,  Michael J. Hargrove

Inventor： Rohit Pal ,  Frank Bin Yang ,  Michael J. Hargrove

IPC: H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7848

Abstract: Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect.

Abstract translation: 提供半导体晶体管器件及相关制造方法。 示例性晶体管器件包括其中限定有沟道区的半导体材料层和覆盖沟道区的栅极结构。 凹槽在与沟道区相邻的半导体材料层中形成，使得凹槽朝向沟道区不对称地延伸。 晶体管器件还包括形成在凹槽中的应力诱导半导体材料。 应力诱导半导体材料的不对称轮廓以不会加剧短通道效应的方式提高载流子迁移率。

公开(公告)号：US08278165B2

公开(公告)日：2012-10-02

申请号：US12577628

申请日：2009-10-12

Applicant: Rohit Pal ,  Janice Monzet

Inventor： Rohit Pal ,  Janice Monzet

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/31111 ,  H01L21/823878

Abstract: Methods for fabricating semiconductor devices are provided. The methods include providing a semiconductor substrate having pFET and nFET regions, each having active areas and shallow trench isolation. A hardmask layer is formed overlying the semiconductor substrate. A photoresist layer is provided over the hardmask layer. The phoresist layer is patterned. An exposed portion of the hardmask layer is removed from one of the pFET region and nFET region with the patterned photoresist acting as an etch mask to define a masked region and an unmasked region. An epitaxial silicon layer is formed on the active area in the unmasked region. A protective oxide layer is formed overlying the epitaxial silicon layer. The hardmask layer is removed from the masked region with the protective oxide layer protecting the epitaxial silicon layer during such removal step. The protective oxide layer is removed from the epitaxial silicon layer.

Abstract translation: 提供制造半导体器件的方法。 所述方法包括提供具有pFET和nFET区域的半导体衬底，每个具有有源区和浅沟槽隔离。 形成覆盖半导体衬底的硬掩模层。 在硬掩模层上提供光致抗蚀剂层。 光刻胶层被图案化。 硬掩模层的暴露部分从pFET区域和nFET区域中的一个去除，图案化的光致抗蚀剂用作蚀刻掩模以限定掩蔽区域和未掩模区域。 在未掩模区域的有源区域上形成外延硅层。 形成覆盖在外延硅层上的保护性氧化物层。 在这种去除步骤期间，保护氧化层保护外延硅层，从屏蔽区域去除硬掩模层。 从外延硅层去除保护氧化物层。

公开(公告)号：US08148750B2

公开(公告)日：2012-04-03

申请号：US13052969

申请日：2011-03-21

Applicant: Rohit Pal ,  Frank Bin Yang ,  Michael J. Hargrove

Inventor： Rohit Pal ,  Frank Bin Yang ,  Michael J. Hargrove

IPC: H01L21/02

CPC classification number: H01L29/66636 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7848

Abstract: Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect.

Abstract translation: 提供半导体晶体管器件及相关制造方法。 示例性晶体管器件包括其中限定有沟道区的半导体材料层和覆盖沟道区的栅极结构。 凹槽在与沟道区相邻的半导体材料层中形成，使得凹槽朝向沟道区不对称地延伸。 晶体管器件还包括形成在凹槽中的应力诱导半导体材料。 应力诱导半导体材料的不对称轮廓以不会加剧短通道效应的方式提高载流子迁移率。