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    Memory expansion and integrated circuit stacking system and method
    13.
    发明申请
    Memory expansion and integrated circuit stacking system and method 有权
    内存扩展和集成电路堆叠系统及方法

    公开(公告)号：US20050057911A1

    公开(公告)日：2005-03-17

    申请号：US10804452

    申请日：2004-03-19

    Applicant: Russell Rapport ,  James Cady ,  James Wilder ,  David Roper ,  James Wehrly ,  Jeff Buchle

    Inventor： Russell Rapport ,  James Cady ,  James Wilder ,  David Roper ,  James Wehrly ,  Jeff Buchle

    IPC: H01L25/065 ,  H01L25/10 ,  H05K7/06 ,  H01L23/538

    CPC classification number: H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/107 ,  H01L2924/3011 ,  H01L2924/00012

    Abstract: The present invention stacks integrated circuits (ICs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In a preferred embodiment of the memory addressing system, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access.

    Abstract translation: 本发明将集成电路（IC）堆叠成节省PWB或其他板表面积的模块。 在另一方面，本发明提供了一种较低电容存储器扩展寻址系统和方法，并且优选地具有本文提供的CSP堆叠模块。 在根据本发明的优选实施例中，形式标准提供了一种物理形式，其允许在广泛的CSP封装系列中发现的许多变化的封装尺寸在使用标准连接柔性电路设计时被有利地使用。 在优选实施例中，将设计形式标准，以便传热材料例如铜，以改善热性能。 在存储器寻址系统的优选实施例中，高速交换系统选择与堆叠模块的每个级别相关联的数据线，以减少对存储器访问中的数据信号的负载影响。

    Memory expansion and chip scale stacking system and method
    18.
    发明授权
    Memory expansion and chip scale stacking system and method 失效
    内存扩展和芯片级堆叠系统及方法

    公开(公告)号：US07256484B2

    公开(公告)日：2007-08-14

    申请号：US10963867

    申请日：2004-10-12

    Applicant: Russell Rapport ,  James W. Cady ,  James Wilder ,  David L. Roper ,  James Douglas Wehrly, Jr. ,  Jeff Buchle

    Inventor： Russell Rapport ,  James W. Cady ,  James Wilder ,  David L. Roper ,  James Douglas Wehrly, Jr. ,  Jeff Buchle

    IPC: H01L23/02

    CPC classification number: H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/50 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01055 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2224/0401

    Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard is disposed between the flex circuitry and the IC package over which a portion of the flex circuitry is laid. The form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In a preferred embodiment, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access. This favorably changes the impedance characteristics exhibited by a DIMM board populated with stacked modules. In a preferred embodiment, FET multiplexers for example, under logic control select particular data lines associated with particular levels of stacked modules populated upon a DIMM for connection to a controlling chip set in a memory expansion system.

    Abstract translation: 本发明将芯片级封装集成电路（CSP）堆叠成保存PWB或其他板表面积的模块。 在另一方面，本发明提供了一种较低电容存储器扩展寻址系统和方法，并且优选地具有本文提供的CSP堆叠模块。 在根据本发明的优选实施例中，形式标准被布置在柔性电路和IC封装之间，柔性电路的一部分放置在该IC封装上。 形式标准提供了一种物理形式，允许在采用标准连接柔性电路设计时，在广泛的CSP封装系列中发现许多变化的封装尺寸。 在优选实施例中，将设计形式标准，以便传热材料例如铜，以改善热性能。 在优选实施例中，高速交换系统选择与堆叠模块的每个级别相关联的数据线，以减少对存储器访问中的数据信号的负载效应。 这有利地改变了堆叠模块的DIMM板所呈现的阻抗特性。 在优选实施例中，例如在逻辑控制下的FET多路复用器选择与填充在DIMM上的特定级别的堆叠模块相关联的特定数据线，以连接到存储器扩展系统中的控制芯片。

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