公开(公告)号：US09384087B2

公开(公告)日：2016-07-05

申请号：US14542828

申请日：2014-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moshe Twitto ,  Avner Dor ,  Jun Jin Kong ,  Jung Soo Chung

IPC: H03M13/03 ,  G06F11/10 ,  H03M13/11 ,  H03M13/37 ,  H03M13/00

CPC classification number: G06F11/1012 ,  G06F11/108 ,  G06F2211/109 ,  H03M13/036 ,  H03M13/1157 ,  H03M13/118 ,  H03M13/373 ,  H03M13/3746 ,  H03M13/611

Abstract: Example embodiments disclose methods and apparatuses for encoding and decoding data in a memory system. In an encoding method according to an example embodiment of inventive concepts, a codeword is generated based on a combination of data to be stored and auxiliary data according to stuck cells and an encoding matrix based on information regarding coordinates of the stuck cells and values of the stuck cells. The generated codeword includes data corresponding to the values of the stuck cells at addresses corresponding to the coordinates of the stuck cells. In a decoding method according to an example embodiment of inventive concepts, data may be generated by multiplying an inverse matrix of the encoding matrix used for encoding by the codeword.

Abstract translation: 示例性实施例公开了用于在存储器系统中对数据进行编码和解码的方法和装置。 在根据发明构思的示例性实施例的编码方法中，基于被存储的数据和辅助数据的组合，根据被卡住的小区和基于关于被卡住的小区的坐标的信息的编码矩阵和 卡住细胞。 生成的码字包括对应于与被卡住的小区的坐标对应的地址处的卡住的小区的值的数据。 在根据发明构思的示例性实施例的解码方法中，可以通过将用于编码的编码矩阵的逆矩阵乘以码字来生成数据。

公开(公告)号：US09202576B2

公开(公告)日：2015-12-01

申请号：US14211077

申请日：2014-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoav Shereshevski ,  Avner Dor ,  Shmuel Dashevsky ,  Jun Jin Kong ,  Pil Sang Yoon

IPC: G11C16/04 ,  G11C16/10 ,  G11C11/56 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/3459

Abstract: A method of programming a non-volatile memory device includes; defining a set of verification voltages, setting a maximum verification voltage among verification voltages that are less than or equal to a first target programming voltage to be a target verification voltage, calculating a number of extra pulses based on the target verification voltage and the first target programming voltage, verifying whether a threshold voltage of the memory cell is equal to or greater than the target verification voltage by applying an incremental step pulse program (ISPP) pulse to the memory cell and then applying at least one verification voltage in the set of verification voltages to the memory cell, and further applying the ISPP pulse to the memory cell a number of times equal to the number of extra pulses when the threshold voltage is verified to be equal to or greater than the target verification voltage.

Abstract translation: 非易失性存储器件的编程方法包括： 定义一组验证电压，将小于或等于第一目标编程电压的验证电压之间的最大验证电压设置为目标验证电压，基于目标验证电压和第一目标计算额外脉冲数 编程电压，通过向存储单元施加增量步进脉冲程序（ISPP）脉冲，然后在验证集合中施加至少一个验证电压来验证存储器单元的阈值电压是否等于或大于目标验证电压 并且当阈值电压被验证为等于或大于目标验证电压时，进一步将ISPP脉冲施加到存储器单元等于额外脉冲数的次数。

公开(公告)号：US11855658B1

公开(公告)日：2023-12-26

申请号：US17882306

申请日：2022-08-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Amit Berman ,  Avner Dor ,  Yaron Shany ,  Ilya Shapir ,  Ariel Doubchak

IPC: H03M13/00 ,  H03M13/15 ,  H03M13/11

CPC classification number: H03M13/1515 ,  H03M13/1108 ,  H03M13/1545 ,  H03M13/1575

Abstract: A processing circuit is configured to: construct a first locator polynomial for a Reed-Solomon codeword to identify locations of erasures in the Reed-Solomon codeword; determine a first syndrome of the Reed-Solomon codeword; calculate a first error evaluator polynomial from the first syndrome and the first locator polynomial; and perform error detection based on the first error evaluator polynomial to determine presence of errors in the Reed-Solomon codeword. When presence of errors in the Reed-Solomon codeword is not detected in the error detection, the processing circuit bypasses updating the first locator polynomial and proceeds to completing decoding of the Reed-Solomon codeword, but when presence of errors in the Reed-Solomon codeword is detected in the error detection, the system first updates the first locator polynomial to a second locator polynomial in a process with reduced complexity compared to the common one, before completing decoding of the Reed-Solomon codeword.

公开(公告)号：US10606760B2

公开(公告)日：2020-03-31

申请号：US15684252

申请日：2017-08-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Elona Erez ,  Avner Dor ,  Moshe Twitto ,  Jun Jin Kong

IPC: G06F12/1009 ,  G06F12/02

Abstract: A memory system includes a nonvolatile memory device having a plurality of physical sectors, a mapping table, and a memory controller including a plurality of hash functions. The memory controller is configured to access the physical sectors using the mapping table and the hash functions. The memory controller is configured to receive a sequence of logical block addresses (LBAs) from a host and logical sector data for each of the LBAs, generate a first virtual address by operating a selected hash function among the hash functions on a first logical block address (LBA) among the sequence, compress the logical sector data to generate compressed data, and store the compressed data in a first physical sector among the physical sectors that is associated with the first virtual address.

公开(公告)号：US10289561B2

公开(公告)日：2019-05-14

申请号：US15671855

申请日：2017-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Elona Erez ,  Avner Dor ,  Jun-Jin Kong

IPC: G06F12/10 ,  G06F12/1009 ,  G06F3/06

Abstract: A method of controlling a nonvolatile memory device includes: receiving a plurality of logical pages associated with a plurality of physical addresses, respectively; storing the plurality of logical pages at the plurality of physical addresses in a selected one of a plurality of sub-clusters according to a given order of logical addresses of the logical pages; generating a first table including an entry for each one of the ordered logical addresses identifying a cluster of the selected sub-cluster and an offset into the selected sub-cluster; and generating a second table including an entry for the selected sub-cluster and the cluster indicating one of the ordered logical addresses associated with a first physical page of the selected sub-cluster.

公开(公告)号：US09483413B2

公开(公告)日：2016-11-01

申请号：US14523159

申请日：2014-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Avner Dor ,  Elona Erez ,  Shay Landis ,  Jun Jin Kong

IPC: G06F12/10

CPC classification number: G06F12/1009 ,  G06F12/0246 ,  G06F2212/152 ,  G06F2212/2022 ,  G06F2212/7201 ,  G06F2212/7203

Abstract: At least one example embodiment discloses a method of controlling a nonvolatile memory device including a plurality of blocks, each block including a plurality of physical pages. The method includes receiving a plurality of logical pages associated with a first plurality of logical addresses, respectively, and writing the first plurality of logical pages to the plurality physical addresses according to an ascending order of the logical addresses of the first plurality of logical pages.

Abstract translation: 至少一个示例性实施例公开了一种控制包括多个块的非易失性存储器件的方法，每个块包括多个物理页。 该方法包括分别接收与第一多个逻辑地址相关联的多个逻辑页面，并根据第一多个逻辑页面的逻辑地址的升序将多个逻辑页面写入多个物理地址。

公开(公告)号：US11942965B1

公开(公告)日：2024-03-26

申请号：US18045576

申请日：2022-10-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Avner Dor ,  Yaron Shany ,  Ariel Doubchak ,  Amit Berman

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G06F13/16 ,  G06F13/28 ,  H03M13/11 ,  H03M13/15

CPC classification number: H03M13/1575 ,  H03M13/1111 ,  H03M13/1545

Abstract: A soft-decision decoding computes a first syndrome polynomial in accordance with a received word, computes a second syndrome polynomial by multiplying the first syndrome polynomial by a locator polynomial based on locations of erasures within the received word, finds a basis and private solution to an affine space of polynomials that solve key equations based on the second syndrome polynomial, determines a weak set of a locations of symbols in the received word with confidence below a certain confidence level, computes a matrix from the basis, the private solution and the weak set, determines sub-matrices in the matrix whose rank is equal to a rank of the matrix, determines error locator polynomial (ELP) candidates from the sub-matrices, the basis, and the private solution, and corrects the received word using a selected one of the ELP candidates.

公开(公告)号：US11689221B1

公开(公告)日：2023-06-27

申请号：US17647441

申请日：2022-01-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Avner Dor ,  Yaron Shany ,  Ariel Doubchak ,  Amit Berman

IPC: H03M13/00 ,  H03M13/15 ,  H03M13/45

CPC classification number: H03M13/152 ,  H03M13/1575 ,  H03M13/458

Abstract: A method for Bose-Chaudhuri-Hocquenghem (BCH) soft error decoding includes receiving a codeword x, wherein the received codeword x has τ=t+r errors for some r≥1; computing a minimal monotone basis {λi(x)}1≤i≤r+1⊆F[x] of an affine space V={λ(x)ϵF[x]: λ(x)·S(x)=λ′(x) (mod x2t), λ(0)=1, deg(λ(x)≤t+r}, wherein λ(x) is an error locator polynomial and S(x) is a syndrome; computing a matrix A≡(λjβi))iϵ[W],jϵ[r+1], wherein W={βi, . . . , βW} is a set of weak bits in x; constructing a submatrix of r+1 rows from sub matrices of r+1 rows of the subsets of A such that the last column is a linear combination of the other columns; forming a candidate error locating polynomial using coefficients of the minimal monotone basis that result from the constructed submatrix; performing a fast Chien search to verify the candidate error locating polynomial; and flipping channel hard decision at error locations found in the candidate error locating polynomial.

公开(公告)号：US11031956B2

公开(公告)日：2021-06-08

申请号：US16452240

申请日：2019-06-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Amit Berman ,  Ariel Doubchak ,  Avner Dor

IPC: H03M13/29 ,  H03M13/15 ,  G06F3/06

Abstract: A method for storing data within a memory device includes receiving data to be stored. The received data is encoded. The encoded data is stored within the memory device. Encoding the received data includes encoding the data into two or more sub-codewords. Each of the two or more sub-codewords includes a plurality of outer codewords. Two or more of the plurality of outer codewords are grouped to form a larger codeword that is larger than each of the plurality of outer codewords and the larger codeword is constructed to correct errors and/or erasures that are not correctable by the plurality of outer codewords, individually.

公开(公告)号：US10528466B2

公开(公告)日：2020-01-07

申请号：US16002151

申请日：2018-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Won Lee ,  Dashevsky Shmuel ,  Moshe Twitto ,  Elona Erez ,  Eran Hof ,  Jun-Jin Kong ,  Avner Dor ,  Michael Erlihson

IPC: G06F12/06 ,  G06F12/1009

Abstract: A method of operating a storage device including a nonvolatile memory can be provided by receiving, from a host, address change information including changing logical addresses for data to be stored in the nonvolatile memory. Physical addresses can be sequentially allocated to the changing logical addresses included in the address change information to provide a first journal. A portion of at least one physical address allocated to the changing logical addresses can be removed to provide a second journal and the second journal can be stored in the nonvolatile memory.