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公开(公告)号：US09384832B2
公开(公告)日：2016-07-05
申请号：US14791636
申请日：2015-07-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyo-Jin Kwon , Yeong-Taek Lee , Dae-Seok Byeon
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C11/1673 , G11C11/56 , G11C13/0004 , G11C13/0007 , G11C2213/72
Abstract: A method is for operating a memory device including a plurality of memory cells disposed in regions where a plurality of first signal lines and a plurality of second signal lines cross each other. The method includes applying an initial voltage to the plurality of first signal lines, floating the plurality of first signal lines to which the initial voltage is applied, applying a second inhibit voltage to the plurality of second signal lines, and increasing voltage levels of the plurality of first signal lines to a first inhibit voltage level via capacitive coupling between the plurality of first signal lines which are floated and the plurality of second signal lines to which the second inhibit voltage is applied.
Abstract translation: 一种用于操作存储器件的方法，该存储器件包括设置在多个第一信号线和多条第二信号线彼此交叉的区域中的多个存储单元。 该方法包括将初始电压施加到多个第一信号线，使施加有初始电压的多条第一信号线浮置，向多条第二信号线施加第二禁止电压，以及增加多个第一信号线的电压电平 的第一信号线通过在浮置的多个第一信号线之间的电容耦合和施加第二禁止电压的多个第二信号线之间的第一禁止电压电平。
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12.发明授权Nonvolatile memory device having read circuits for performing Read-While-Write (RWW) operation and Read-Modify-Write (RMW) operation 有权具有用于执行读写（RWW）操作和读取 - 修改 - 写入（RMW）操作的读取电路的非易失性存储器件公开(公告)号：US09135994B2
公开(公告)日：2015-09-15
申请号：US14171873
申请日：2014-02-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyo-Jin Kwon , Hoi-Ju Chung , Chae-Hoon Kim , Yong-Jin Kwon , Eun-Hye Park , Yong-Jun Lee
CPC classification number: G11C13/004 , G11C13/0002 , G11C13/0004 , G11C13/0061 , G11C2213/72
Abstract: A nonvolatile memory device includes a memory array having multiple nonvolatile memory cells, a first read circuit and a second read circuit. The first read circuit is configured to read first data from the memory array during a first read operation and to provide one or more protection signals indicating a victim period during the first read operation. The second read circuit is configured to read second data from the memory array during a second read operation and to provide one or more check signals indicating an aggressor period during the second read operation.
Abstract translation: 非易失性存储器件包括具有多个非易失性存储单元的存储器阵列，第一读取电路和第二读取电路。 第一读取电路被配置为在第一读取操作期间从存储器阵列读取第一数据，并且在第一读取操作期间提供指示受害时段的一个或多个保护信号。 第二读取电路被配置为在第二读取操作期间从存储器阵列读取第二数据，并且在第二读取操作期间提供指示侵略者周期的一个或多个检查信号。
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13.发明申请NONVOLATILE MEMORY DEVICE USING A RESISTANCE MATERIAL AND A DRIVING METHOD THEREOF 有权使用电阻材料的非易失性存储器件及其驱动方法公开(公告)号：US20150003137A1
公开(公告)日：2015-01-01
申请号：US14317162
申请日：2014-06-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yong-Jun Lee , Hoi-Ju Chung , Yong-Jin Kwon , Hyo-Jin Kwon , Eun-Hye Park
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C7/1039 , G11C7/1042 , G11C11/5678 , G11C11/5685 , G11C13/0061 , G11C2213/71 , G11C2213/72
Abstract: A nonvolatile memory device includes a buffer memory, a read circuit configured to read first data stored in the buffer memory in a first read operation, and a write circuit configured to write second data in the buffer memory in a first write operation, wherein the first write operation is performed when a first internal write command is generated during the first read operation.
Abstract translation: 非易失性存储器件包括缓冲存储器，被配置为在第一读取操作中读取存储在缓冲存储器中的第一数据的读取电路和被配置为在第一写入操作中将第二数据写入缓冲存储器的写入电路，其中第一 在第一读取操作期间产生第一内部写入命令时执行写入操作。
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14.发明授权Resistive memory device having memory cell arrays with multiple stack layers and bad-region managing circuit and method for managing short failure 有权具有具有多个堆叠层的存储单元阵列和不良区域管理电路的电阻式存储器件以及用于管理短路故障的方法公开(公告)号：US09570200B2
公开(公告)日：2017-02-14
申请号：US14743521
申请日：2015-06-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyo-Jin Kwon , Dae-Seok Byeon , Yeong-Taek Lee , Chi-Weon Yoon , Yong-Kyu Lee , Hyun-Kook Park
CPC classification number: G11C29/76 , G11C11/16 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1677 , G11C11/1695 , G11C13/0002 , G11C13/0023 , G11C13/0059 , G11C13/0064 , G11C13/0069 , G11C29/808 , G11C2029/4402 , G11C2213/71
Abstract: A resistive memory device includes a memory cell array that includes a plurality of memory layers stacked in a vertical direction. Each of the plurality of memory layers includes a plurality of memory cells disposed in regions where a plurality of first lines and a plurality of second lines cross each other. A bad region management unit defines as a bad region a first memory layer including a bad cell from among the plurality of memory cells and at least one second memory layer.
Abstract translation: 电阻式存储器件包括存储单元阵列，其包括沿垂直方向堆叠的多个存储层。 多个存储层中的每一个包括设置在多个第一线和多条第二线彼此交叉的区域中的多个存储单元。 不良区域管理单元将包括来自多个存储器单元中的不良单元和至少一个第二存储器层的第一存储器层定义为不良区域。
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Patent Agency Ranking
公开(公告)号：US09472275B2
公开(公告)日：2016-10-18
申请号：US14698175
申请日：2015-04-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyun-Kook Park , Young-Hoon Oh , Dae-Seok Byeon , Yong-Kyu Lee , Hyo-Jin Kwon
CPC classification number: G11C13/004 , G06F11/00 , G06F11/1048 , G11C11/1659 , G11C11/1673 , G11C13/0004 , G11C13/0007 , G11C13/0033 , G11C2013/0045 , G11C2013/0054
Abstract: A memory device and a method of operating the memory device are provided for performing a read-retry operation. The method of operating the memory device includes starting a read-retry mode, reading data of multiple cell regions using different read conditions, and setting a final read condition for the cell regions according to results of data determination operations on data read from the cell regions.
Abstract translation: 提供了一种用于执行读取重试操作的存储器件和操作存储器件的方法。 操作存储装置的方法包括开始读取重试模式，使用不同的读取条件读取多个单元区域的数据，并且根据从单元区域读取的数据的数据确定操作的结果来设置单元区域的最终读取条件 。
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16.发明授权Resistive memory device and method of operating the same to reduce leakage current 有权电阻式存储器件及其操作方法，以减少漏电流公开(公告)号：US09361974B2
公开(公告)日：2016-06-07
申请号：US14683269
申请日：2015-04-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yong-Kyu Lee , Dae-Seok Byeon , Yeong-Taek Lee , Chi-Weon Yoon , Hyun-Kook Park , Hyo-Jin Kwon
CPC classification number: G11C13/0023 , G11C13/0033 , G11C13/0038 , G11C13/004 , G11C13/0069 , G11C2013/0045 , G11C2013/0078
Abstract: A method of operating a memory device includes determining a value of an operating current flowing through a selected first signal line, to which a selection voltage is applied, from among a plurality of first signal lines; dividing an array of memory cells into n blocks, n being an integer greater than 1, based on the value of the operating current; and applying inhibit voltages having different voltage levels corresponding to the n blocks to unselected ones of second signal lines included in the n blocks. Each of the unselected second signal lines is a pathway through which leakage current may potentially flow due to the operating current flowing through the selected first signal line and a memory cell addressed by the unselected second signal line and the selected first signal line.
Abstract translation: 一种操作存储器件的方法包括从多个第一信号线中确定流过所选择的第一信号线的工作电流的值，所述第一信号线被施加选择电压; 将存储单元阵列划分为n个块，n是大于1的整数，基于工作电流的值; 以及将对应于n个块的具有不同电压电平的抑制电压施加到包括在n个块中的未选择的第二信号线。 每个未选择的第二信号线是由于流过所选择的第一信号线的工作电流和由未选择的第二信号线和所选择的第一信号线寻址的存储器单元而引起的漏电流可能流过的通路。
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17.发明授权Nonvolatile memory device using a resistance material and a driving method thereof 有权使用电阻材料的非易失性存储器件及其驱动方法公开(公告)号：US09299429B2
公开(公告)日：2016-03-29
申请号：US14317162
申请日：2014-06-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yong-Jun Lee , Hoi-Ju Chung , Yong-Jin Kwon , Hyo-Jin Kwon , Eun-Hye Park
CPC classification number: G11C13/004 , G11C7/1039 , G11C7/1042 , G11C11/5678 , G11C11/5685 , G11C13/0061 , G11C2213/71 , G11C2213/72
Abstract: A nonvolatile memory device includes a buffer memory, a read circuit configured to read first data stored in the buffer memory in a first read operation, and a write circuit configured to write second data in the buffer memory in a first write operation, wherein the first write operation is performed when a first internal write command is generated during the first read operation.
Abstract translation: 非易失性存储器件包括缓冲存储器，被配置为在第一读取操作中读取存储在缓冲存储器中的第一数据的读取电路和被配置为在第一写入操作中将第二数据写入缓冲存储器的写入电路，其中第一 在第一读取操作期间产生第一内部写入命令时执行写入操作。
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18.发明授权Resistive memory device, resistive memory system, and method of operating resistive memory device 有权电阻式存储器件，电阻式存储器系统和操作电阻式存储器件的方法公开(公告)号：US09269429B2
公开(公告)日：2016-02-23
申请号：US14665127
申请日：2015-03-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyun-Kook Park , Dae-Seok Byeon , Yeong-Taek Lee , Bo-Geun Kim , Yong-Kyu Lee , Hyo-Jin Kwon
CPC classification number: G11C13/0069 , G11C5/025 , G11C13/0023 , G11C13/0033 , G11C2213/71
Abstract: A resistive memory device includes a memory cell array including a plurality vertically stacked layers having one layer designated as an interference-free layer and another layer designated as an access prohibited layer, wherein the interference-free layer and the access prohibited layer share a connection with at least one signal line and access operations directed to memory cells the access prohibited layer are prohibited.
Abstract translation: 电阻式存储器件包括存储单元阵列，该存储单元阵列包括多个垂直层叠的层，其中一层被指定为无干扰层，另一层指定为禁止访问层，其中无干扰层和禁止访问层共享与 禁止至少一条信号线和针对存储器单元访问禁止层的访问操作。
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19.发明授权公开(公告)号：US09093146B2
公开(公告)日：2015-07-28
申请号：US14171849
申请日：2014-02-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Eun-Hye Park , Hoi-Ju Chung , Yong-Jin Kwon , Hyo-Jin Kwon , Yong-Jun Lee
CPC classification number: G11C13/0061 , G11C13/0002 , G11C13/004 , G11C2213/72
Abstract: A nonvolatile memory device comprises a memory core comprising a plurality of variable resistance memory cells, an input/output (I/O) circuit configured to receive a first packet signal and a second packet signal in sequence, the first and second packet signals collectively comprising information for a memory access operation, and further configured to initiate a core access operation upon decoding the first packet signal and to selectively continue or discontinue the core access operation upon decoding the second packet signal, and a read circuit configured to perform part of the core access operation in response to the first packet signal before the second packet signal is decoded.
Abstract translation: 非易失性存储器件包括存储器芯，其包括多个可变电阻存储器单元，输入/输出（I / O）电路被配置为依次接收第一分组信号和第二分组信号，第一和第二分组信号共同地包括 用于存储器访问操作的信息，并且还被配置为在解码所述第一分组信号时发起核心访问操作，并且在解码所述第二分组信号时选择性地继续或中断所述核心访问操作;以及读取电路，被配置为执行所述核心的一部分 在第二分组信号被解码之前响应于第一分组信号的接入操作。
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