公开(公告)号：US12230329B2

公开(公告)日：2025-02-18

申请号：US17953003

申请日：2022-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunhyang Park ,  Joonsuc Jang ,  Se Hwan Park ,  Ji-Sang Lee

IPC: G11C16/08 ,  G11C16/10 ,  G11C16/28 ,  G11C16/34

Abstract: A flash memory device includes a memory cell array connected with word lines and control logic that performs threshold voltage compensation on the word lines through a data recover read operation. When a word line on which programming is performed after a selected word line is a dummy word line, the control logic performs the threshold voltage compensation on the selected word line based on a result of a data recover read operation of a word line on which programming is performed before the selected word line. When a next word line on which programming is performed after a selected word line is a dummy word line, the control logic performs threshold voltage compensation on the selected word line based on a result of performing the data recover read operation on a previous word line on which programming is performed before the selected word line.

公开(公告)号：US20230154552A1

公开(公告)日：2023-05-18

申请号：US17847545

申请日：2022-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junho Kim ,  Jinyoung Kim ,  Sehwan Park ,  Seoyoung Lee ,  Jisang Lee ,  Joonsuc Jang

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08

CPC classification number: G11C16/3459 ,  G11C16/3404 ,  G11C16/102 ,  G11C16/26 ,  G11C16/08

Abstract: Aggressor memory cells connected to one or more aggressor wordlines are grouped into aggressor cell groups by performing a read operation with respect to the aggressor wordlines based on one or more grouping read voltages, where the aggressor wordlines are adjacent to a selected wordline corresponding to a read address among wordlines of a memory block. Selected memory cells connected to the selected wordline are grouped into a selected cell groups respectively corresponding to the aggressor cell groups. Group read conditions respectively corresponding to the selected cell groups are determined and group read operations are performed with respect to the plurality of selected cell groups based on the group read conditions. The read errors are reduced by grouping the selected memory cells into the selected cell groups according to the change of operation environments.

公开(公告)号：US11309032B2

公开(公告)日：2022-04-19

申请号：US17077200

申请日：2020-10-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonsuc Jang

IPC: G11C16/10 ,  G06F3/06 ,  G06F11/10 ,  G11C11/56 ,  G11C16/08 ,  G11C16/26 ,  G11C16/34 ,  G11C16/04

Abstract: An operating method of a memory system includes preprogramming multi-page data of a memory controller to a nonvolatile memory device, generating a state group code based on multi-bit data of the multi-page data, and each state group data of the state group code having less number of bits than corresponding multi-bit data, detecting sudden power-off occurring after the preprogramming, backing up, in response to the detecting of the sudden power-off occurring, the state group code to the nonvolatile memory device, recovering, after power is recovered from the sudden power-off, the multi-page data from the nonvolatile memory device, based on the state group code, reprogramming the multi-page data to the nonvolatile memory device, and reprogramming, in response to the detecting of the sudden power-off not occurring, the multi-page data of the memory controller to the nonvolatile memory device.

公开(公告)号：US20210158874A1

公开(公告)日：2021-05-27

申请号：US17077200

申请日：2020-10-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonsuc Jang

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/26 ,  G11C16/08 ,  G11C16/34 ,  G06F3/06 ,  G06F11/10

Abstract: An operating method of a memory system includes preprogramming multi-page data of a memory controller to a nonvolatile memory device, generating a state group code based on multi-bit data of the multi-page data, and each state group data of the state group code having less number of bits than corresponding multi-bit data, detecting sudden power-off occurring after the preprogramming, backing up, in response to the detecting of the sudden power-off occurring, the state group code to the nonvolatile memory device, recovering, after power is recovered from the sudden power-off, the multi-page data from the nonvolatile memory device, based on the state group code, reprogramming the multi-page data to the nonvolatile memory device, and reprogramming, in response to the detecting of the sudden power-off not occurring, the multi-page data of the memory controller to the nonvolatile memory device.

公开(公告)号：US20250118381A1

公开(公告)日：2025-04-10

申请号：US18899546

申请日：2024-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungmin Park ,  Sion Kim ,  Joonsuc Jang

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10

Abstract: An example operating method of a nonvolatile memory device includes applying a first verification voltage to selected memory cells in a first program loop that verifies pass or fail of a first program state among a plurality of program states, applying a second verification voltage to the selected memory cells in the first program loop that verifies pass or fail of a second program state among the plurality of program states, applying a program voltage to the selected memory cells in a second program loop, and verifying, based on the program voltage being applied to the selected memory cells, pass or fail of the first program state and the second program state for the selected memory cells based on a result of applying the first verification voltage and a result of applying the second verification voltage.

公开(公告)号：US20240249782A1

公开(公告)日：2024-07-25

申请号：US18423047

申请日：2024-01-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minkyeong CHOI ,  Joonsuc Jang ,  Ji-Sang Lee

IPC: G11C16/34 ,  G11C16/04

CPC classification number: G11C16/349 ,  G11C16/0483

Abstract: A memory system includes: a memory device including a memory cell array and a control circuit; and a temperature sensor configured to measure a temperature of the memory device to generate a temperature value, wherein the control circuit is configured to: set a compensation sensing parameter based on the temperature value, determine a sensing parameter by applying the compensation sensing parameter to a basic sensing parameter corresponding to a read mode among a plurality of read modes having different read speeds, and read data from the memory cell array based on the sensing parameter.

公开(公告)号：US12040020B2

公开(公告)日：2024-07-16

申请号：US17854163

申请日：2022-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwangho Choi ,  Minseok Kim ,  Il Han Park ,  Jun-Yong Park ,  Joonsuc Jang

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/12 ,  G11C16/26

CPC classification number: G11C16/0433 ,  G11C16/08 ,  G11C16/12 ,  G11C16/26

Abstract: Disclosed is a memory device which includes a history table and communicates with a storage controller. A method of operating the memory device includes receiving a first request indicating a first core operation of a first memory block from the storage controller, determining whether history data of the first memory block have a first value or a second value, with reference to the history table, in response to the first request, when it is determined that the history data of the first memory block have the first value, performing the first core operation corresponding to a first type on the first memory block, and after performing the first core operation corresponding to the first type on the first memory block, updating the history data of the first memory block in the history table from the first value to the second value.

公开(公告)号：US11915763B2

公开(公告)日：2024-02-27

申请号：US17698056

申请日：2022-03-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonsuc Jang

IPC: H04L1/00 ,  G06F11/00 ,  G06F11/30 ,  G08C25/00 ,  H03M13/00 ,  G11C16/10 ,  G06F3/06 ,  G06F11/10 ,  G11C11/56 ,  G11C16/08 ,  G11C16/26 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C16/10 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0644 ,  G06F3/0647 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1068 ,  G11C11/56 ,  G11C16/08 ,  G11C16/26 ,  G11C16/3459 ,  G11C16/0483

Abstract: An operating method of a memory system includes preprogramming multi-page data of a memory controller to a nonvolatile memory device, generating a state group code based on multi-bit data of the multi-page data, and each state group data of the state group code having less number of bits than corresponding multi-bit data, detecting sudden power-off occurring after the preprogramming, backing up, in response to the detecting of the sudden power-off occurring, the state group code to the nonvolatile memory device, recovering, after power is recovered from the sudden power-off, the multi-page data from the nonvolatile memory device, based on the state group code, reprogramming the multi-page data to the nonvolatile memory device, and reprogramming, in response to the detecting of the sudden power-off not occurring, the multi-page data of the memory controller to the nonvolatile memory device.

公开(公告)号：US11823753B2

公开(公告)日：2023-11-21

申请号：US18128596

申请日：2023-03-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonsuc Jang ,  Hyunggon Kim ,  Sangbum Yun ,  Dongwook Kim ,  Kyungsoo Park ,  Sejin Baek

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C7/10 ,  G11C16/24

CPC classification number: G11C16/3459 ,  G11C7/106 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1087 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

Abstract: A method of programming a nonvolatile memory device includes performing a single-pulse program operation in a program loop, determining whether a condition is satisfied in the a program loop, and performing a multi-pulse program operation in a next program loop when the condition is satisfied. The single-pulse program operation includes applying a first program pulse and applying plural verification pulses, the multi-pulse program operation includes applying a second program pulse, applying a third program pulse, and applying plural verification pulses, and each of the second program pulse and the third program pulse has a level lower than a level of the first program pulse.

公开(公告)号：US11562804B2

公开(公告)日：2023-01-24

申请号：US17469422

申请日：2021-09-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sehwan Park ,  Jinyoung Kim ,  Youngdeok Seo ,  Dongmin Shin ,  Joonsuc Jang ,  Sungmin Joe

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/18 ,  G11C16/10 ,  G11C29/12 ,  G11C16/26

Abstract: A storage device includes a nonvolatile memory device and a memory controller to control the nonvolatile memory device. The nonvolatile memory device includes a memory cell array. The memory cell array includes a normal cell region, a parity cell region and a redundancy cell region. First bit-lines are connected to the normal cell region and the parity cell region and second bit-lines are connected to the redundancy cell region. The memory controller includes an error correction code (ECC) engine to generate parity data. The memory controller stores user data in the normal cell region, controls the nonvolatile memory device to perform a column repair on first defective bit-lines among the first bit-lines, assigns additional column addresses to the first defective bit-lines and the second bit-lines and stores at least a portion of the parity data in a region corresponding to the additionally assigned column addresses.