公开(公告)号：US20180287634A1

公开(公告)日：2018-10-04

申请号：US15475602

申请日：2017-03-31

Applicant: SanDisk Technologies LLC

Inventor： Rami Rom ,  Idan Goldenberg ,  Alexander Bazarsky ,  Eran Sharon ,  Ran Zamir ,  Idan Alrod ,  Stella Achtenberg

IPC: H03M13/11 ,  H03M13/00

CPC classification number: H03M13/118 ,  G06F3/0619 ,  G06F3/0655 ,  G06F3/0688 ,  G06F11/10 ,  G06F11/1048 ,  H03M13/1102 ,  H03M13/1125 ,  H03M13/116 ,  H03M13/3715 ,  H03M13/616 ,  H03M13/6516 ,  H03M13/6566

Abstract: A storage device may program data differently for different memory areas of a memory. In some embodiments, the storage device may use different codebooks for different memory areas. In other embodiments, the storage device may modify bit orders differently for different memory areas. What codebook the storage device uses or what bit order modification the storage device performs for a particular memory area may depend on the bad storage locations specific to that memory area. Where different codebooks are used, optimal codebooks may be selected from a library, or codebooks may be modified based on the bad storage locations of the memory areas.

公开(公告)号：US10090044B2

公开(公告)日：2018-10-02

申请号：US15215862

申请日：2016-07-21

Applicant: SanDisk Technologies LLC

Inventor： Stella Achtenberg ,  Alon Eyal ,  Eran Sharon

IPC: G11C29/00 ,  G11C11/56 ,  G11C16/10 ,  G11C16/16 ,  G06F11/10 ,  G11C29/52

Abstract: A memory system can program data in different modes, such as normal mode programming and burst mode programming. Burst mode programming programs data into the memory device faster than normal mode programming. MLC Blocks for burst mode programming are selected based on one or more criteria, such as block age, block programming speed, or the like. Further, one or more burst mode TRIM settings, which include one or more of a program voltage TRIM setting, a step-up voltage TRIM setting, skip verify level, and a program pulse width, are used to program the blocks selected for burst mode programming. In this regard, burst mode programming is performed more quickly than normal mode programming.

公开(公告)号：US10002086B1

公开(公告)日：2018-06-19

申请号：US15385324

申请日：2016-12-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Stella Achtenberg ,  Eran Sharon ,  Ran Zamir ,  Amir Shaharabany

IPC: H03M13/00 ,  G06F13/16 ,  G06F13/40 ,  G06F11/10 ,  G11C29/52 ,  H03M13/11 ,  G06F3/06

Abstract: In an illustrative example, a device includes a memory and a controller that is coupled to the memory and that is configured to communicate with the memory using at least a first channel and a second channel. The controller includes a bit error rate (BER) estimator configured to estimate a first BER corresponding to the first channel and a second BER corresponding to the second channel. The controller also includes a throughput balancer configured to determine whether to adjust at least one of a first clock rate of the first channel or a second clock rate of the second channel based on the first BER and the second BER.

公开(公告)号：US20180025776A1

公开(公告)日：2018-01-25

申请号：US15215862

申请日：2016-07-21

Applicant: SanDisk Technologies LLC

Inventor： Stella Achtenberg ,  Alon Eyal ,  Eran Sharon

IPC: G11C11/56 ,  G11C29/52 ,  G06F11/10 ,  G11C16/10 ,  G11C16/16

CPC classification number: G11C11/5628 ,  G06F11/1072 ,  G11C7/1018 ,  G11C16/10 ,  G11C16/16 ,  G11C16/32 ,  G11C29/021 ,  G11C29/028 ,  G11C29/42 ,  G11C29/52 ,  G11C2029/0411 ,  G11C2211/5641

Abstract: Apparatus and method for performing burst mode programming in a memory system are disclosed. A memory system may program data in different modes, such as normal mode programming and burst mode programming. Burst mode programming programs data into the memory device faster than normal mode programming. MLC Blocks for burst mode programming may be selected based on one or more criteria, such as block age, block programming speed, or the like. Further, one or more burst mode TRIM settings, which may include a program voltage TRIM setting, a step-up voltage TRIM setting, skip verify level, and a program pulse width, may be used to program the blocks selected for burst mode programming. In this regard, burst mode programming may be performed more quickly than normal mode programming.

公开(公告)号：US10236909B2

公开(公告)日：2019-03-19

申请号：US15475666

申请日：2017-03-31

Applicant: SanDisk Technologies LLC

Inventor： Rami Rom ,  Idan Goldenberg ,  Alexander Bazarsky ,  Eran Sharon ,  Ran Zamir ,  Idan Alrod ,  Stella Achtenberg

IPC: H03M13/11 ,  H03M13/00 ,  G06F3/06

Abstract: A storage device may program data differently for different memory areas of a memory. In some embodiments, the storage device may use different codebooks for different memory areas. In other embodiments, the storage device may modify bit orders differently for different memory areas. What codebook the storage device uses or what bit order modification the storage device performs for a particular memory area may depend on the bad storage locations specific to that memory area. Where different codebooks are used, optimal codebooks may be selected from a library, or codebooks may be modified based on the bad storage locations of the memory areas.

公开(公告)号：US10158380B2

公开(公告)日：2018-12-18

申请号：US15371167

申请日：2016-12-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Eran Sharon ,  Alexander Bazarsky ,  Idan Goldenberg ,  Stella Achtenberg ,  Omer Fainzilber ,  Ran Zamir

IPC: G11C29/00 ,  H03M13/00 ,  G06F3/06 ,  G06F11/10 ,  H03M13/29

Abstract: A device includes a memory and a controller coupled to the memory. The controller is configured to determine a first count of bits of a representation of data that are estimated to be erroneous and a second count of bits of the representation of data that have high estimated reliability and are estimated to be erroneous. The controller is further configured to modify at least one read parameter or at least one decode parameter based on the first count and the second count.

公开(公告)号：US10116333B2

公开(公告)日：2018-10-30

申请号：US15223531

申请日：2016-07-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ran Zamir ,  Alexander Bazarsky ,  Stella Achtenberg ,  Omer Fainzilber ,  Eran Sharon

IPC: H03M13/11 ,  G11C16/08 ,  G06F11/10 ,  H03M13/00 ,  G11C16/16 ,  G11C16/26 ,  G11C16/10 ,  G11C11/56 ,  G11C16/04

Abstract: A device includes a memory configured to store syndromes, a first data processing unit coupled to the memory, and a second data processing unit coupled to the memory. The first data processing unit is configured to process a first value corresponding to a first symbol of data to be decoded. The second data processing unit is configured to process a second value corresponding to a second symbol of the data. Syndrome aggregation circuitry is coupled to the first data processing unit and to the second data processing unit. The syndrome aggregation circuitry is configured to combine syndrome change decisions of the first data processing unit and the second data processing unit.