公开(公告)号：US20210408035A1

公开(公告)日：2021-12-30

申请号：US17038870

申请日：2020-09-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jo SATO ,  Kota FUNAYAMA ,  Tatsuya HINOUE

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524

Abstract: A lower source-level dielectric etch-stop layer, a source-level sacrificial layer, and an upper source-level dielectric etch-stop layer are formed over a substrate. An alternating stack of insulating layers and sacrificial material layers is formed thereabove. Memory stack structures are formed through the alternating stack. Backside openings are formed through the alternating stack and into the in-process source-level material layers such that tapered surfaces are formed through the upper source-level dielectric etch-stop layer. A source cavity is formed by removing the source-level sacrificial layer, and a continuous source contact layer is formed in the source cavity and in peripheral portions of the backside openings. Portions of the continuous source contact layer overlying the tapered surfaces are removed by performing an isotropic etch process. Remaining portions of the continuous source contact layer comprise a source contact layer. The sacrificial material layers are replaced with electrically conductive layers.

公开(公告)号：US20240213147A1

公开(公告)日：2024-06-27

申请号：US18355067

申请日：2023-07-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Naohiro HOSODA ,  Tatsuya HINOUE

IPC: H01L23/522 ,  H01L23/528 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/5226 ,  H01L23/5283 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A three-dimensional memory device may be formed by forming a vertically alternating sequence of insulating layers and sacrificial material layers over a substrate, forming memory openings, forming sacrificial memory opening fill structures in the memory openings, forming first cavities by removing a first subset of the sacrificial memory opening fill structures, forming laterally-extending cavities by performing an isotropic etch process that laterally recesses the sacrificial material layers, forming electrically conductive layers in the laterally-extending cavities, forming second cavities by removing the second subset of the sacrificial memory opening fill structures, and forming memory opening fill structures in each of the first cavities and the second cavities.

公开(公告)号：US20240096695A1

公开(公告)日：2024-03-21

申请号：US17932907

申请日：2022-09-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Michiaki SANO ,  Tatsuya HINOUE

IPC: H01L21/768 ,  H01L21/311

CPC classification number: H01L21/76831 ,  H01L21/31144 ,  H01L21/76805 ,  H01L21/76843

Abstract: A conductive hard mask layer can be patterned with peripheral discrete openings. An anisotropic etch process can be performed to form peripheral discrete via cavities, which are subsequently expanded to form a continuous moat trench. An edge seal structure can be formed in the continuous moat trench. Alternatively, a conductive bridge structure may be formed prior to formation of a patterned conductive hard mask layer, and a moat trench can be formed around a periphery of the semiconductor die while the conductive bridge structure provides electrical connection between an inner portion and an outer portion of the conductive hard mask layer. The entire conductive hard mask layer can be electrically connected to a semiconductor substrate to reduce or prevent arcing during an anisotropic etch process that forms the peripheral discrete via cavities or the moat trench.

公开(公告)号：US20230130849A1

公开(公告)日：2023-04-27

申请号：US18059698

申请日：2022-11-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takashi YAMAHA ,  Tatsuya HINOUE ,  Fumitaka AMANO

IPC: H01L23/535 ,  H01L23/532 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/768

Abstract: A metal interconnect assembly includes a first metal interconnect structure, and a second metal interconnect structure embedded in a second dielectric material layer and containing a metal line portion having a top surface located within a first horizontal plane and having a bottom surface located within a second horizontal plane, and further containing a metal via portion adjoined to a bottom of the metal line portion and contacting a top surface of the first metal interconnect structure. The second metal interconnect structure contains a metallic liner including a first metallic material that includes an entire volume of the metal via portion and an outer part of the metal line portion, and a metallic fill material portion contains a second metallic material that includes an inner part of the metal line portion, does not contact and is spaced from the second dielectric material layer by the metallic liner.

公开(公告)号：US20230128441A1

公开(公告)日：2023-04-27

申请号：US17507224

申请日：2021-10-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masanori TSUTSUMI ,  Yusuke MUKAE ,  Tatsuya HINOUE ,  Yuki KASAI

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11565 ,  G11C16/04

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and memory stack structures extending through the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel, a tunneling dielectric layer, a vertical stack of discrete silicon nitride memory elements located at levels of the electrically conductive layers, and a vertical stack of discrete silicon oxide blocking dielectric structures laterally surrounding the vertical stack of discrete silicon nitride memory elements. Each of the silicon oxide blocking dielectric structures includes a silicon oxynitride surface region, and an atomic concentration of nitrogen atoms within the silicon oxynitride surface region decreases with a lateral distance from an interface between the silicon oxynitride surface region and a respective one of the silicon nitride memory elements.

公开(公告)号：US20230069170A1

公开(公告)日：2023-03-02

申请号：US17465131

申请日：2021-09-02

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tatsuya HINOUE

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L29/792

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. The sacrificial material layers include a stack of word-line-level sacrificial material layers and at least one drain-select-level sacrificial material layer. Drain-select-level openings are formed through the at least one drain-select-level sacrificial material layer, which is replaced with at least one drain-select-level electrically conductive layer. Memory openings are formed by vertically extending the drain-select-level openings through the word-line-level sacrificial material layers. Memory opening fill structures are formed within the memory openings. The word-line-level sacrificial material layers are replaced with word-line-level electrically conductive layers.

公开(公告)号：US20220406794A1

公开(公告)日：2022-12-22

申请号：US17406493

申请日：2021-08-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tatsuya HINOUE ,  Naoki TAKEGUCHI

IPC: H01L27/1157 ,  H01L27/11565 ,  H01L27/11582 ,  G11C16/04

Abstract: A three-dimensional memory device includes a vertical repetition of multiple instances of a unit layer stack, memory openings vertically extending through the vertical repetition, and memory opening fill structures located within the memory openings. Each of the memory opening fill structures contains a respective vertical stack of memory elements. The unit layer stack includes, from bottom to top or from top to bottom, a cavity-free insulating layer that is free of any cavity therein, a first-type electrically conductive layer, a cavity-containing insulating layer including an encapsulated cavity therein, and a second-type electrically conductive layer.

公开(公告)号：US20220406793A1

公开(公告)日：2022-12-22

申请号：US17351756

申请日：2021-06-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Naoki TAKEGUCHI ,  Masanori TSUTSUMI ,  Seiji SHIMABUKURO ,  Tatsuya HINOUE

IPC: H01L27/1157 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565

Abstract: A vertical repetition of multiple instances of a unit layer stack is formed over a substrate. The unit layer stack includes an insulating layer and a sacrificial material layer. Lateral recesses are formed by removing the sacrificial material layers selective to the insulating layers. Each lateral recess is sequentially fill with at least one conductive fill material and an insulating fill material, and vertically-extending portions of the at least one conductive fill material are removed such that a vertical layer stack including a first-type electrically conductive layer, a seamed insulating layer, and a second-type electrically conductive layer are formed in each lateral recess. Memory opening fill structures including a respective vertical stack of memory elements is formed through the insulating layers and the layer stacks. Access points for providing an etchant for removing the sacrificial material layers may be provided by memory openings, contact via cavities or backside trenches.

公开(公告)号：US20240260266A1

公开(公告)日：2024-08-01

申请号：US18356896

申请日：2023-07-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Naohiro HOSODA ,  Masanori TSUTSUMI ,  Shunsuke TAKUMA ,  Seiji SHIMABUKURO ,  Tatsuya HINOUE ,  Takashi KASHIMURA ,  Tomohiro KUBO ,  Hisakazu OTOI ,  Hiroyuki TANAKA ,  Takumi MORIYAMA ,  Ryota SUZUKI

IPC: H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B43/35

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers, such that a first electrically conductive layer of the electrically conductive layers is in contact with an underlying silicon oxycarbide liner and with an overlying silicon oxycarbide liner, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a memory film containing a continuous memory material layer which continuously extends through the entire alternating stack.

公开(公告)号：US20240099014A1

公开(公告)日：2024-03-21

申请号：US18524552

申请日：2023-11-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shunsuke TAKUMA ,  Yuji TOTOKI ,  Seiji SHIMABUKURO ,  Tatsuya HINOUE ,  Kengo KAJIWARA ,  Akihiro TOBIOKA

IPC: H10B43/50 ,  H01L23/00 ,  H01L23/522 ,  H10B41/27 ,  H10B41/50 ,  H10B43/27

CPC classification number: H10B43/50 ,  H01L23/5226 ,  H01L23/562 ,  H10B41/27 ,  H10B41/50 ,  H10B43/27

Abstract: At least one vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate. Rows of backside support pillar structures are formed through the at least one vertically alternating sequence. Memory stack structures are formed through the at least one vertically alternating sequence. A two-dimensional array of discrete backside trenches is formed through the at least one vertically alternating sequence. Contiguous combinations of a subset of the backside trenches and a subset of the backside support pillar structures divide the at least one vertically alternating sequence into alternating stacks of insulating layers and sacrificial material layers. The sacrificial material layers are replaced with electrically conductive layers while the backside support pillar structures provide structural support to the insulating layers.