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    FANOUT WAFER LEVEL PACKAGE FOR OPTICAL DEVICES AND RELATED METHODS
    13.
    发明申请
    FANOUT WAFER LEVEL PACKAGE FOR OPTICAL DEVICES AND RELATED METHODS 有权

    公开(公告)号：US20210167112A1

    公开(公告)日：2021-06-03

    申请号：US16701533

    申请日：2019-12-03

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Yusheng LIN ,  Takashi NOMA

    IPC: H01L27/146

    Abstract: Implementations of semiconductor packages may include: a substrate having a first side and a second side. The package may include a semiconductor package and a controller device coupled to the first side of the substrate through a tape or an adhesive. A molding compound may encapsulate the semiconductor device and the controller device. The package may also include a redistribution layer electrically coupling the semiconductor device and the controller device. An interconnect structure may be coupled with the redistribution layer. The package may include a solder resist layer coupled around the interconnect structure and over the molding compound, the semiconductor device, the controller device, and the copper redistribution layer.

    METHODS OF ALIGNING A SEMICONDUCTOR WAFER FOR SINGULATION
    14.
    发明申请
    METHODS OF ALIGNING A SEMICONDUCTOR WAFER FOR SINGULATION 有权

    公开(公告)号：US20210028064A1

    公开(公告)日：2021-01-28

    申请号：US17068129

    申请日：2020-10-12

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Michael J. SEDDON ,  Takashi NOMA

    IPC: H01L21/78 ,  H01L21/66 ,  H01L21/3205 ,  H01L21/683 ,  H01L21/02 ,  H01L21/304

    Abstract: Implementations of a method for aligning a semiconductor wafer for singulation may include: providing a semiconductor wafer having a first side and a second side. The first side of the wafer may include a plurality of die and the plurality of die may be separated by streets. The semiconductor wafer may include an edge ring around a perimeter of the wafer on the second side of the wafer. The wafer may also include a metal layer on the second side of the wafer. The metal layer may substantially cover the edge ring. The method may include grinding the edge ring to create an edge exclusion area and aligning the semiconductor wafer with a saw using a camera positioned in the edge exclusion area on the second side of the wafer. Aligning the wafer may include using three or more alignment features included in the edge exclusion area.

    SEMICONDUCTOR BACKMETAL (BM) AND OVER PAD METALLIZATION (OPM) STRUCTURES AND RELATED METHODS
    15.
    发明申请
    SEMICONDUCTOR BACKMETAL (BM) AND OVER PAD METALLIZATION (OPM) STRUCTURES AND RELATED METHODS 审中-公开

    公开(公告)号：US20180005951A1

    公开(公告)日：2018-01-04

    申请号：US15448008

    申请日：2017-03-02

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Yusheng LIN ,  Takashi NOMA ,  Shinzo ISHIBE

    IPC: H01L23/532 ,  H01L23/528 ,  H01L29/739 ,  H01L29/861 ,  H01L23/00

    Abstract: A method of forming semiconductor devices includes providing a wafer having a first side and second side, electrically conductive pads at the second side, and an electrically insulative layer at the second side with openings to the pads. The first side of the wafer is background to a desired thickness and an electrically conductive layer is deposited thereon. Nickel layers are simultaneously electrolessly deposited over the electrically conductive layer and over the pads, and diffusion barrier layers are then simultaneously deposited over the nickel layers. Another method of forming semiconductor devices includes depositing backmetal (BM) layers on the electrically conductive layer including a titanium layer, a nickel layer, and/or a silver layer. The BM layers are covered with a protective coating and a nickel layer is electrolessly deposited over the pads. A diffusion barrier layer is deposited over the nickel layer over the pads, and the protective coating is removed.

    SEMICONDUCTOR WAFER AND METHOD OF BALL DROP ON THIN WAFER WITH EDGE SUPPORT RING
    16.
    发明申请
    SEMICONDUCTOR WAFER AND METHOD OF BALL DROP ON THIN WAFER WITH EDGE SUPPORT RING 有权

    公开(公告)号：US20250062263A1

    公开(公告)日：2025-02-20

    申请号：US18939985

    申请日：2024-11-07

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Michael J. SEDDON ,  Takashi NOMA ,  Kazuhiro SAITO

    IPC: H01L23/00 ,  B23K3/06 ,  H01L21/48

    Abstract: A semiconductor wafer has an edge support ring around a perimeter of the semiconductor wafer and conductive layer formed over a surface of the semiconductor wafer within the edge support ring. A first stencil is disposed over the edge support ring with first openings aligned with the conductive layer. The first stencil includes a horizontal portion over the edge support ring, and a step-down portion extending the first openings to the conductive layer formed over the surface of the semiconductor wafer. The horizontal portion may have a notch with the edge support ring disposed within the notch. A plurality of bumps is dispersed over the first stencil to occupy the first openings over the conductive layer. A second stencil is disposed over the edge support ring with second openings aligned with the conductive layer to deposit a flux material in the second openings over the conductive layer.

    MULTI-CHIP SYSTEM-IN-PACKAGE
    18.
    发明申请
    MULTI-CHIP SYSTEM-IN-PACKAGE 有权

    公开(公告)号：US20220359360A1

    公开(公告)日：2022-11-10

    申请号：US17661420

    申请日：2022-04-29

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Yusheng LIN ,  Takashi NOMA

    IPC: H01L23/498 ,  H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L21/768 ,  H01L25/00

    Abstract: A system-in-package includes an interposer substrate having a first side and a second side opposite the first side, and a redistribution layer disposed on the first side. The redistribution layer includes a plurality of contact pads and a plurality of interconnections disposed on the first side. The plurality of interconnections is electrically connected to a plurality of terminals disposed on the second side opposite the first side. A first semiconductor die is disposed on the first side and electrically coupled to a first of the plurality of contact pads and a first of the plurality of interconnections disposed on the first side of the interposer substrate. A second semiconductor die is disposed on the first side. The second semiconductor die is electrically coupled to a second of the plurality of contact pads and a second of the plurality of interconnections disposed on the first side of the interposer substrate.

    METHODS OF ALIGNING A SEMICONDUCTOR WAFER FOR SINGULATION
    20.
    发明申请
    METHODS OF ALIGNING A SEMICONDUCTOR WAFER FOR SINGULATION 有权

    公开(公告)号：US20220172994A1

    公开(公告)日：2022-06-02

    申请号：US17651610

    申请日：2022-02-18

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Michael J. SEDDON ,  Takashi NOMA

    IPC: H01L21/78 ,  H01L21/66 ,  H01L21/3205 ,  H01L21/683 ,  H01L21/02 ,  H01L21/304

    Abstract: Implementations of a method for aligning a semiconductor wafer for singulation may include: providing a semiconductor wafer having a first side and a second side. The first side of the wafer may include a plurality of die and the plurality of die may be separated by streets. The semiconductor wafer may include an edge ring around a perimeter of the wafer on the second side of the wafer. The wafer may also include a metal layer on the second side of the wafer. The metal layer may substantially cover the edge ring. The method may include grinding the edge ring to create an edge exclusion area and aligning the semiconductor wafer with a saw using a camera positioned in the edge exclusion area on the second side of the wafer. Aligning the wafer may include using three or more alignment features included in the edge exclusion area.

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