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    POWER MODULE STRUCTURE WITH CLIP SUBSTRATE MEMBER
    11.
    发明申请
    POWER MODULE STRUCTURE WITH CLIP SUBSTRATE MEMBER 有权

    公开(公告)号：US20250105200A1

    公开(公告)日：2025-03-27

    申请号：US18473998

    申请日：2023-09-25

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Seokbong KIM ,  Byoungok LEE ,  Yong LIU

    IPC: H01L23/00 ,  H01L25/00 ,  H01L25/07

    Abstract: A power module includes a substrate, a plurality of semiconductor dies coupled to the substrate, and a clip substrate member having a first surface and a second surface. The first surface is coupled to the plurality of semiconductor dies. The clip substrate member includes a first conductive clip, and a second conductive clip, and a dielectric material portion disposed between the first conductive clip and the second conductive clip. The second surface includes a first contact region and a second contact region. The first contact region includes a portion of the first conductive clip. The second contact region includes a portion of the second conductive clip.

    DUAL-SIDE COOLING SEMICONDUCTOR PACKAGES AND RELATED METHODS
    14.
    发明公开
    DUAL-SIDE COOLING SEMICONDUCTOR PACKAGES AND RELATED METHODS 审中-公开

    公开(公告)号：US20230238307A1

    公开(公告)日：2023-07-27

    申请号：US18194780

    申请日：2023-04-03

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Yong LIU ,  Qing YANG

    IPC: H01L23/492 ,  H01L23/00 ,  H01L23/373

    CPC classification number: H01L23/4922 ,  H01L24/48 ,  H01L23/3735 ,  H01L24/32 ,  H01L2224/32258 ,  H01L2224/48245 ,  H01L23/3107

    Abstract: A dual-side cooling (DSC) semiconductor package includes a first metal-insulator-metal (MIM) substrate having a first insulator layer, first metallic layer, and second metallic layer. A second MIM substrate includes a second insulator layer, third metallic layer, and fourth metallic layer. The third metallic layer includes a first portion having a first contact area and a second portion, electrically isolated from the first portion, having a second contact area. A semiconductor die is coupled with the second metallic layer and is directly coupled with the third metallic layer through one or more solders, sintered layers, electrically conductive tapes, solderable top metal (STM) layers, and/or under bump metal (UBM) layers. The first contact area is electrically coupled with a first electrical contact of the die and the second contact area is electrically coupled with a second electrical contact of the die. The first and fourth metallic layers are exposed through an encapsulant.

    POWER MODULE
    16.
    发明申请
    POWER MODULE 有权

    公开(公告)号：US20220130740A1

    公开(公告)日：2022-04-28

    申请号：US16949262

    申请日：2020-10-22

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Qing YANG ,  Yong LIU ,  Yushuang YAO

    IPC: H01L23/498 ,  H01L25/18 ,  H01L21/48 ,  H01L25/07 ,  H01L23/00 ,  H01L23/32 ,  H01L23/373

    Abstract: A power module can include a casing mounted to a baseplate that contains a substrate with circuitry. The circuitry can include pins for coupling signals to/from the circuitry. These pins can extend through a cover portion of the casing so that an electronic substrate, such as a printed circuit board (PCB) can be press-fit onto the pins. When press-fit, the electronic substrate is supported and positioned by support pillars that extend from the base plate to above the cover portion of the casing. If the pins and the support pillars have different coefficients of thermal expansion, damage to connection points between the pins and the circuitry may occur. Here, a power module is disclosed that has thermally matched pins and support pillars so that when the system is thermally cycled over a range of temperatures, the connection points are not damaged by forces induced by thermal expansion.

    LEADFRAME SPACER FOR DOUBLE-SIDED POWER MODULE
    17.
    发明申请
    LEADFRAME SPACER FOR DOUBLE-SIDED POWER MODULE 有权

    公开(公告)号：US20210398874A1

    公开(公告)日：2021-12-23

    申请号：US17447011

    申请日：2021-09-07

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Tzu-Hsuan CHENG ,  Yong LIU ,  Liangbiao CHEN

    IPC: H01L23/367 ,  H01L21/52 ,  H01L21/56 ,  H01L23/373 ,  H01L23/495 ,  H05K7/20 ,  H01L23/00

    Abstract: A semiconductor device module may include a leadframe spacer that provides the functions of both a leadframe and a spacer, while enabling a double-sided cooling configuration. Such a leadframe spacer may include a leadframe surface that provides a die attach pad (DAP) that is shared by at least two semiconductor devices. The leadframe spacer may include at least one downset, where the semiconductor devices may be attached within a recess defined by the at least one downset. A first substrate may be connected to a first side of the leadframe. A second substrate may be connected to downset surfaces of the at least one downset, and positioned for further connection to the semiconductor devices in a double-sided assembly.

    FLIP CHIP AND PRE-MOLDED CLIP POWER MODULES
    18.
    发明申请
    FLIP CHIP AND PRE-MOLDED CLIP POWER MODULES 有权

    公开(公告)号：US20250006603A1

    公开(公告)日：2025-01-02

    申请号：US18344292

    申请日：2023-06-29

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Yong LIU ,  Qing YANG

    IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

    Abstract: Devices and methods are disclosed for high power inverter modules with enhanced thermal and mechanical performance, for use in electric vehicles. The disclosed devices feature enlarged clips that cover an entire die, to distribute mechanical forces, thus preventing die cracks for improved reliability. In these power modules, semiconductor dies are sandwiched between a three-layer direct bond metal (DBM) structure and the enlarged clip. A pre-molded clip assembly can be used that includes integrated metalliization to eliminate the need for external wire bonds. Alternatively, semiconductor dies can be inverted in a flip-chip configuration to face a modified DBM structure that integrates the metallization. Simulations of the disclosed power inverters indicate improved efficiency in dissipating heat.

    SEMICONDUCTOR PACKAGES AND RELATED METHODS
    19.
    发明公开
    SEMICONDUCTOR PACKAGES AND RELATED METHODS 审中-公开

    公开(公告)号：US20240355638A1

    公开(公告)日：2024-10-24

    申请号：US18760515

    申请日：2024-07-01

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Yong LIU ,  Yusheng LIN ,  Liangbiao CHEN

    IPC: H01L21/48 ,  H01L21/56 ,  H01L23/28 ,  H01L23/495 ,  H01L23/498

    CPC classification number: H01L21/4821 ,  H01L21/56 ,  H01L23/28 ,  H01L23/49534 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49861

    Abstract: Methods of forming semiconductor packages include providing a first insulator layer coupled with a first metallic layer. A recess is formed in the first metallic layer and a semiconductor die is mechanically coupled therein. The die is mechanically coupled with a second metallic layer and the second metallic layer is coupled with a second insulator layer. The die and layers are at least partially encapsulated to form the semiconductor package. The first and/or second metallic layers may be insulator-metal substrates, metal-insulator-metal (MIM) substrates, or may be formed of lead frames. In implementations the package does not include a spacer between the die and the first metallic layer and does not include a spacer between the die and the second metallic layer. In implementations the first insulator layer and the second insulator layer are exposed through the encapsulant or are mechanically coupled with metallic layers exposed through the encapsulant.

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