公开(公告)号：US09029863B2

公开(公告)日：2015-05-12

申请号：US13860894

申请日：2013-04-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsuo Isobe

IPC: H01L29/12 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/66969 ,  H01L21/70 ,  H01L27/1085 ,  H01L27/1259 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A variation in electrical characteristics, such as a negative shift of the threshold voltage or an increase in S value, of a fin-type transistor including an oxide semiconductor material is prevented. An oxide semiconductor film is sandwiched between a plurality of gate electrodes with an insulating film provided between the oxide semiconductor film and each of the gate electrodes. Specifically, a first gate insulating film is provided to cover a first gate electrode, an oxide semiconductor film is provided to be in contact with the first gate insulating film and extend beyond the first gate electrode, a second gate insulating film is provided to cover at least the oxide semiconductor film, and a second gate electrode is provided to be in contact with part of the second gate insulating film and extend beyond the first gate electrode.

Abstract translation: 防止包括氧化物半导体材料的鳍式晶体管的电特性的变化，例如阈值电压的负偏移或S值的增加。 氧化物半导体膜被夹在多个栅电极之间，其间具有设置在氧化物半导体膜和每个栅电极之间的绝缘膜。 具体地，设置第一栅极绝缘膜以覆盖第一栅电极，设置氧化物半导体膜以与第一栅极绝缘膜接触并且延伸超过第一栅电极，设置第二栅极绝缘膜以覆盖在 至少设置氧化物半导体膜，第二栅电极与第二栅极绝缘膜的一部分接触并且延伸超过第一栅电极。

公开(公告)号：US08785259B2

公开(公告)日：2014-07-22

申请号：US13722028

申请日：2012-12-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Ryota Imahayashi ,  Shinobu Furukawa ,  Atsuo Isobe ,  Yasuyuki Arai ,  Shunpei Yamazaki

IPC: H01L21/00

CPC classification number: H01L51/0512 ,  H01L21/02175 ,  H01L21/02244 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/31683 ,  H01L51/0002 ,  H01L51/0055 ,  H01L51/0525 ,  H01L51/0541 ,  H01L51/0545 ,  H01L51/0566

Abstract: It is an object to form a high quality gate insulating film which is dense and has a strong insulation resistance property, and to propose a high reliable organic transistor in which a tunnel leakage current is little. One mode of the organic transistor of the present invention has a step of forming the gate insulating film by forming the conductive layer which becomes the gate electrode activating oxygen (or gas including oxygen) or nitrogen (or gas including nitrogen) or the like using dense plasma in which density of electron is 1011 cm−3 or more, and electron temperature is a range of 0.2 eV to 2.0 eV with plasma activation, and reacting directly with a portion of the conductive layer which becomes the gate electrode to be insulated.

Abstract translation: 本发明的目的是形成致密且具有很强绝缘电阻特性的高质量栅极绝缘膜，并且提出了隧道泄漏电流很小的高可靠性有机晶体管。 本发明的有机晶体管的一种模式具有如下步骤：通过使用密集的方法形成作为活化氧（或含氧气体）或氮（或含氮气体）的栅极的导电层形成栅极绝缘膜 电子密度为1011cm -3以上的等离子体，等离子体活化时电子温度为0.2eV〜2.0eV的范围，直接与成为要被绝缘的栅电极的导体层的一部分反应。

公开(公告)号：US11823036B2

公开(公告)日：2023-11-21

申请号：US17588613

申请日：2022-01-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko Ishizu ,  Takayuki Ikeda ,  Atsuo Isobe ,  Atsushi Miyaguchi ,  Shunpei Yamazaki

IPC: G06T1/20 ,  G06F1/3234 ,  G06N3/065 ,  G06F7/544

CPC classification number: G06N3/065 ,  G06F1/3243 ,  G06F7/5443 ,  G06T1/20

Abstract: An arithmetic device and an electronic device having small power consumption is provided. An arithmetic device and an electronic device capable of high-speed operation is provided. An arithmetic device and an electronic device capable of suppressing heat generation is provided. The arithmetic device includes a first arithmetic portion and a second arithmetic portion. The first arithmetic portion includes a first CPU core and a second CPU core. The second arithmetic portion includes a first GPU core and a second GPU core. The CPU cores each have a power gating function and each include a first data retention circuit electrically connected to a flip-flop. The first GPU core includes a second data retention circuit capable of retaining an analog value and reading out the analog value as digital data of two or more bits. The second GPU core includes a third data retention circuit capable of retaining a digital value and reading out the digital value as digital data of one bit. The first to third data retention circuits each include a transistor including an oxide semiconductor and a capacitor.

公开(公告)号：US11374023B2

公开(公告)日：2022-06-28

申请号：US17083393

申请日：2020-10-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Wataru Uesugi ,  Hikaru Tamura ,  Atsuo Isobe

IPC: H03K19/173 ,  H01L27/12 ,  H01L29/786 ,  H01L49/02 ,  H01L29/04 ,  H01L29/78 ,  H03K19/00 ,  H03K19/0185 ,  G11C7/04

Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.

公开(公告)号：US10910404B2

公开(公告)日：2021-02-02

申请号：US16256348

申请日：2019-01-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshinori Ieda ,  Atsuo Isobe ,  Yutaka Shionoiri ,  Tomoaki Atsumi

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/423 ,  H01L29/49 ,  H01L29/16 ,  H01L29/04 ,  H01L29/78 ,  H01L27/092 ,  H01L27/105 ,  H01L49/02 ,  H01L27/115 ,  H01L27/108 ,  H01L29/24 ,  H01L27/11551 ,  H01L27/1156

Abstract: Provided is a semiconductor device which has low power consumption and can operate at high speed. The semiconductor device includes a memory element including a first transistor including crystalline silicon in a channel formation region, a capacitor for storing data of the memory element, and a second transistor which is a switching element for controlling supply, storage, and release of charge in the capacitor. The second transistor is provided over an insulating film covering the first transistor. The first and second transistors have a source electrode or a drain electrode in common.

公开(公告)号：US10388670B2

公开(公告)日：2019-08-20

申请号：US15447672

申请日：2017-03-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshinori Ieda ,  Atsuo Isobe ,  Yutaka Shionoiri ,  Tomoaki Atsumi

IPC: H01L27/105 ,  H01L27/12 ,  H01L29/16 ,  H01L29/04 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L27/092 ,  H01L27/108 ,  H01L27/115 ,  H01L49/02 ,  H01L29/24 ,  H01L27/1156 ,  H01L27/11551

Abstract: Provided is a semiconductor device which has low power consumption and can operate at high speed. The semiconductor device includes a memory element including a first transistor including crystalline silicon in a channel formation region, a capacitor for storing data of the memory element, and a second transistor which is a switching element for controlling supply, storage, and release of charge in the capacitor. The second transistor is provided over an insulating film covering the first transistor. The first and second transistors have a source electrode or a drain electrode in common.

公开(公告)号：US10068890B2

公开(公告)日：2018-09-04

申请号：US15667672

申请日：2017-08-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hikaru Tamura ,  Naoaki Tsutsui ,  Atsuo Isobe

IPC: H01L25/00 ,  H01L27/02 ,  H01L27/12 ,  H01L27/06 ,  H01L23/528 ,  H01L23/532 ,  H01L29/786 ,  H03K19/00

Abstract: To provide a semiconductor device including element layers that are stacked. A first wiring layer and a second wiring layer are stacked between a first element layer and a second element layer. A third wiring layer and a fourth wiring layer are stacked over the second element layer. Transistors of logic cells are provided in the first element layer. Wirings of the logic cells are provided in the first wiring layer or the second wiring layer. Input ports and output ports of the logic cells are provided in the third wiring layer. The input port of one of the logic cells is connected to the output port of another logic cell through the wiring of the third wiring layer or the fourth wiring layer. Connecting the logic cells through the wiring layers over the second element layer improves the efficiency of steps of arranging and connecting the logic cells.

公开(公告)号：US10008587B2

公开(公告)日：2018-06-26

申请号：US14459597

申请日：2014-08-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Atsuo Isobe ,  Toshihiko Saito ,  Takehisa Hatano ,  Hideomi Suzawa ,  Shinya Sasagawa ,  Junichi Koezuka ,  Yuichi Sato ,  Shinji Ohno

IPC: H01L21/336 ,  H01L21/311 ,  H01L29/786 ,  H01L29/66 ,  H01L27/12 ,  H01L21/02 ,  H01L21/31

CPC classification number: H01L29/66969 ,  H01L21/02488 ,  H01L21/02565 ,  H01L27/1225 ,  H01L29/786 ,  H01L29/78606 ,  H01L29/7869

Abstract: A semiconductor device which includes an oxide semiconductor and has favorable electrical characteristics is provided. In the semiconductor device, an oxide semiconductor film and an insulating film are formed over a substrate. Side surfaces of the oxide semiconductor film are in contact with the insulating film. The oxide semiconductor film includes a channel formation region and regions containing a dopant between which the channel formation region is sandwiched. A gate insulating film is formed on and in contact with the oxide semiconductor film. A gate electrode with sidewall insulating films is formed over the gate insulating film. A source electrode and a drain electrode are formed in contact with the oxide semiconductor film and the insulating film.

公开(公告)号：US09729148B2

公开(公告)日：2017-08-08

申请号：US15014081

申请日：2016-02-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hikaru Tamura ,  Naoaki Tsutsui ,  Atsuo Isobe

IPC: H01L25/00 ,  H03K19/00 ,  H01L29/786 ,  H01L27/06 ,  H01L27/12 ,  H01L27/02

CPC classification number: H01L27/0207 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53257 ,  H01L27/0688 ,  H01L27/1207 ,  H01L27/1274 ,  H01L29/7869 ,  H03K19/0008

Abstract: To provide a semiconductor device including element layers that are stacked. A first wiring layer and a second wiring layer are stacked between a first element layer and a second element layer. A third wiring layer and a fourth wiring layer are stacked over the second element layer. Transistors of logic cells are provided in the first element layer. Wirings of the logic cells are provided in the first wiring layer or the second wiring layer. Input ports and output ports of the logic cells are provided in the third wiring layer. The input port of one of the logic cells is connected to the output port of another logic cell through the wiring of the third wiring layer or the fourth wiring layer. Connecting the logic cells through the wiring layers over the second element layer improves the efficiency of steps of arranging and connecting the logic cells.

公开(公告)号：US09660095B2

公开(公告)日：2017-05-23

申请号：US14459523

申请日：2014-08-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsuo Isobe ,  Toshinari Sasaki

IPC: H01L21/70 ,  H01L29/786 ,  H01L27/1156 ,  H01L27/12 ,  H01L29/423 ,  H01L23/00 ,  H01L29/04

CPC classification number: H01L29/78696 ,  H01L21/02565 ,  H01L21/02592 ,  H01L21/02667 ,  H01L23/564 ,  H01L27/1052 ,  H01L27/1156 ,  H01L27/1225 ,  H01L29/045 ,  H01L29/24 ,  H01L29/4236 ,  H01L29/42384 ,  H01L29/51 ,  H01L29/66969 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Stable electric characteristics and high reliability are provided to a miniaturized and integrated semiconductor device including an oxide semiconductor. In a transistor (a semiconductor device) including an oxide semiconductor film, the oxide semiconductor film is provided along a trench (groove) formed in an insulating layer. The trench includes a lower end corner portion having a curved shape with a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm, and the oxide semiconductor film is provided in contact with a bottom surface, the lower end corner portion, and an inner wall surface of the trench. The oxide semiconductor film includes a crystal having a c-axis substantially perpendicular to a surface at least over the lower end corner portion.