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    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    11.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
    半导体器件及其制造方法

    公开(公告)号：US20140151675A1

    公开(公告)日：2014-06-05

    申请号：US14174494

    申请日：2014-02-06

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Toshihiko SAITO

    IPC: H01L27/28

    CPC classification number: H01L27/28 ,  G11C5/025 ,  G11C8/08 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1255 ,  H01L28/40

    Abstract: An object of the invention is to reduce an area occupied by a capacitor in a circuit in a semiconductor device, and to downsize a semiconductor device on which the capacitor and an organic memory are mounted. The organic memory and the capacitor, included in a peripheral circuit, in which the same material as the layer containing the organic compound used for the organic memory is used as a dielectric, are used. The peripheral circuit here means a circuit having at least a capacitor such as a resonance circuit, a power supply circuit, a boosting circuit, a DA converter, or a protective circuit. Further, a capacitor in which a semiconductor is used as a dielectric may be provided over the same substrate as well as the capacitor in which the same material as the layer containing the organic compound is used as a dielectric. In this case, it is desirable that the capacitor in which the same material as the layer containing the organic compound is used as a dielectric and the capacitor in which the semiconductor is used as a dielectric are connected to each other in parallel.

    Abstract translation: 本发明的一个目的是减少半导体器件的电路中的电容器所占的面积，并且减小其上安装有电容器和有机存储器的半导体器件。 使用包含在外围电路中的有机存储器和电容器，其中与用于有机存储器的有机化合物的层相同的材料用作电介质。 这里的外围电路是指至少具有诸如谐振电路，电源电路，升压电路，DA转换器或保护电路的电容器的电路。 此外，可以在与使用与含有有机化合物的层相同的材料作为电介质的电容器的同一基板上设置将半导体用作电介质的电容器。 在这种情况下，希望使用与含有有机化合物的层相同的材料作为电介质的电容器和将半导体用作电介质的电容器彼此并联连接。

    METHOD FOR DRIVING SEMICONDUCTOR MEMORY DEVICE
    14.
    发明申请
    METHOD FOR DRIVING SEMICONDUCTOR MEMORY DEVICE 有权
    驱动半导体存储器件的方法

    公开(公告)号：US20150262644A1

    公开(公告)日：2015-09-17

    申请号：US14726756

    申请日：2015-06-01

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Toshihiko SAITO

    IPC: G11C11/407

    CPC classification number: G11C11/407 ,  G11C11/405 ,  G11C11/40615 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3431

    Abstract: A method for driving a semiconductor memory device including a transistor with low leakage current between a source and a drain in an off state and capable of storing data for a long time is provided. In a matrix including a plurality of memory cells in each of which a drain of a write transistor, a gate of an element transistor, and one electrode of a capacitor are connected, a gate of the write transistor is connected to a write word line, and the other electrode of the capacitor is connected to a read word line. The amount of charge stored in the capacitor is checked by changing the potential of the read word line, and if the amount of charge has decreased beyond a predetermined amount, the memory cell is refreshed.

    Abstract translation: 提供了一种用于驱动半导体存储器件的方法，该半导体存储器件包括在断开状态下的源极和漏极之间具有低漏电流的晶体管，并且能够长时间存储数据。 在包括写入晶体管的漏极，元件晶体管的栅极和电容器的一个电极的多个存储单元的矩阵中，写入晶体管的栅极连接到写入字线， 并且电容器的另一个电极连接到读取字线。 通过改变读取字线的电位来检查存储在电容器中的电荷量，并且如果电荷量已经减少超过预定量，则刷新存储器单元。

    SEMICONDUCTOR DEVICE
    15.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20140014955A1

    公开(公告)日：2014-01-16

    申请号：US14031132

    申请日：2013-09-19

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Toshihiko SAITO

    IPC: H01L27/088 ,  H01L29/786

    CPC classification number: H01L27/1052 ,  H01L27/088 ,  H01L27/11524 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1251 ,  H01L27/1255 ,  H01L29/0649 ,  H01L29/247 ,  H01L29/42328 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696 ,  H01L29/788

    Abstract: At least one of a plurality of transistors which are highly integrated in an element is provided with a back gate without increasing the number of manufacturing steps. In an element including a plurality of transistors which are longitudinally stacked, at least a transistor in an upper portion includes a metal oxide having semiconductor characteristics, a same layer as a gate electrode of a transistor in a lower portion is provided to overlap with a channel formation region of the transistor in an upper portion, and part of the same layer as the gate electrode functions as a back gate of the transistor in an upper portion. The transistor in a lower portion which is covered with an insulating layer is subjected to planarization treatment, whereby the gate electrode is exposed and connected to a layer functioning as source and drain electrodes of the transistor in an upper portion.

    Abstract translation: 高度集成在元件中的多个晶体管中的至少一个设置有后栅，而不增加制造步骤的数量。 在包括纵向层叠的多个晶体管的元件中，上部的至少一个晶体管包括具有半导体特性的金属氧化物，与下部晶体管的栅电极相同的层被设置为与沟道重叠 上部的晶体管的形成区域和与栅极电极相同的层的一部分用作上部晶体管的背栅极。 被覆盖有绝缘层的下部的晶体管进行平坦化处理，从而使栅电极暴露并连接到作为上部晶体管的源电极和漏电极的层。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    17.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20130092925A1

    公开(公告)日：2013-04-18

    申请号：US13632635

    申请日：2012-10-01

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Toshihiko SAITO ,  Atsuo ISOBE ,  Kazuya HANAOKA ,  Junichi KOEZUKA ,  Shinya SASAGAWA ,  Motomu KURATA ,  Akihiro ISHIZUKA

    IPC: H01L29/786 ,  H01L29/66

    CPC classification number: H01L29/66477 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693

    Abstract: A miniaturized transistor is provided with high yield. Further, a semiconductor device which has high on-state characteristics and which is capable of high-speed response and high-speed operation is provided. In the semiconductor device, an oxide semiconductor layer, a gate insulating layer, a gate electrode layer, an insulating layer, a conductive film, and an interlayer insulating layer are stacked in this order. A source electrode layer and a drain electrode layer are formed in a self-aligned manner by cutting the conductive film so that the conductive film over the gate electrode layer and the conductive layer is removed and the conductive film is divided. An electrode layer which is in contact with the oxide semiconductor layer and overlaps with a region in contact with the source electrode layer and the drain electrode layer is provided.

    Abstract translation: 提供了一种小型化的晶体管，其产率高。 此外，提供了具有高导通状态特性并且能够进行高速响应和高速操作的半导体器件。 在半导体装置中，依次层叠氧化物半导体层，栅极绝缘层，栅极电极层，绝缘层，导电膜和层间绝缘层。 通过切割导电膜以自对准的方式形成源电极层和漏电极层，从而去除栅极电极层和导电层上的导电膜，并且导电膜被分割。 设置与氧化物半导体层接触并与与源极电极层和漏极电极层接触的区域重叠的电极层。

    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
    18.
    发明申请
    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250113480A1

    公开(公告)日：2025-04-03

    申请号：US18893067

    申请日：2024-09-23

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Toshihiko SAITO ,  Yasuhiro JINBO ,  Shunpei YAMAZAKI

    IPC: H10B12/00

    Abstract: A semiconductor device with a high operation speed is provided. The semiconductor device includes a second oxide semiconductor; a second conductor; a third conductor; a first insulator over the second oxide semiconductor, the second conductor, and the third conductor; a second insulator and a fourth conductor in a first opening portion of the first insulator; and a third insulator and a fifth conductor in a second opening portion of the first insulator. The second oxide semiconductor is formed by removing a region covering the top surface of a columnar insulator from a first oxide semiconductor formed to cover the columnar insulator. The second conductor and the third conductor are formed by sequentially forming a first conductor and a first insulator over the second oxide semiconductor and removing a region overlapping with the second opening portion of the first insulator from the first conductor to expose the second oxide semiconductor. The first opening portion of the first insulator includes a region overlapping with the third conductor and the second oxide semiconductor.

    MEMORY DEVICE AND ELECTRONIC DEVICE
    19.
    发明申请
    MEMORY DEVICE AND ELECTRONIC DEVICE 有权

    公开(公告)号：US20210257020A1

    公开(公告)日：2021-08-19

    申请号：US16972696

    申请日：2019-06-13

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Takahiko ISHIZU ,  Toshihiko SAITO ,  Hideki UOCHI ,  Shunpei YAMAZAKI

    IPC: G11C11/419 ,  H01L29/786 ,  H01L29/04 ,  G11C11/409

    Abstract: A novel memory device is provided. The memory device includes a plurality of memory cells, and one memory cell includes a first transistor and a second transistor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor through a node SN. Data written through the first transistor is retained at the node SN. When an OS transistor is used as the first transistor, formation of a storage capacitor is not needed. A region with a low dielectric constant is provided outside the memory cell, whereby noise from the outside is reduced and stable operation is achieved.

    SEMICONDUCTOR DEVICE AND OPERATION METHOD THEREOF, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE
    20.
    发明申请
    SEMICONDUCTOR DEVICE AND OPERATION METHOD THEREOF, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE 审中-公开

    公开(公告)号：US20190355397A1

    公开(公告)日：2019-11-21

    申请号：US16475906

    申请日：2018-01-09

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Takahiko ISHIZU ,  Toshihiko SAITO

    IPC: G11C5/14 ,  G11C14/00 ,  G06F1/3234

    Abstract: Power consumption of a semiconductor device is reduced efficiently. The semiconductor device includes a power management unit, a cell array, and a peripheral circuit for driving the cell array. The cell array includes a word line, a bit line pair, a memory cell, and a backup circuit for backing up data in the memory cell. A row circuit and a column circuit are provided in a first power domain capable of power gating, and the cell array is provided in a second power domain capable of power gating. In the operation mode of a memory device, a plurality of low power consumption modes, which have lower power consumption than the standby mode, are set. The power management unit selects one from the plurality of low power consumption modes and performs control for bringing the memory device into the selected low power consumption mode.

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