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    Split Gate Non-volatile Memory Cell Having A Floating Gate, Word Line, Erase Gate, And Method Of Manufacturing
    13.
    发明申请
    Split Gate Non-volatile Memory Cell Having A Floating Gate, Word Line, Erase Gate, And Method Of Manufacturing 有权
    具有浮动门，字线，擦除门和制造方法的分离门非易失性存储单元

    公开(公告)号：US20170012049A1

    公开(公告)日：2017-01-12

    申请号：US15182527

    申请日：2016-06-14

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Jeng-Wei Yang ,  Man-Tang Wu ,  Chun-Ming Chen ,  Mandana Tadayoni ,  Chien-Sheng Su ,  Nhan Do

    IPC: H01L27/115 ,  G11C16/26 ,  H01L29/788 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28

    CPC classification number: H01L27/11524 ,  G11C16/26 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7883

    Abstract: A memory device including a silicon semiconductor substrate, spaced apart source and drain regions formed in the substrate with a channel region there between, and a conductive floating gate disposed over a first portion of the channel region and a first portion of the source region. An erase gate includes a first portion that is laterally adjacent to the floating gate and over the source region, and a second portion that extends up and over the floating gate. A conductive word line gate is disposed over a second portion of the channel region. The word line gate is disposed laterally adjacent to the floating gate and includes no portion disposed over the floating gate. The thickness of insulation separating the word line gate from the second portion of the channel region is less than that of insulation separating the floating gate from the erase gate.

    Abstract translation: 一种存储器件，包括硅半导体衬底，形成在衬底中的间隔开的源极和漏极区域，其间具有沟道区域，以及布置在沟道区域的第一部分和源极区域的第一部分之间的导电浮动栅极。 擦除栅极包括横向邻近浮动栅极并在源极区域上方的第一部分，以及在浮动栅极上方和上方延伸的第二部分。 导电字线栅极设置在沟道区域的第二部分上。 字线栅极横向地布置在浮动栅极附近，并且不包括设置在浮动栅极上的部分。 将字线栅极与沟道区域的第二部分分开的绝缘层的厚度小于将浮栅与擦除栅极分开的绝缘层的厚度。

    Split Gate Non-volatile Flash Memory Cell Having Metal Gates And Method Of Making Same
    14.
    发明申请
    Split Gate Non-volatile Flash Memory Cell Having Metal Gates And Method Of Making Same 有权
    具有金属门的分流门非易失性闪存单元及其制作方法

    公开(公告)号：US20160197088A1

    公开(公告)日：2016-07-07

    申请号：US14589650

    申请日：2015-01-05

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Chun-Ming Chen ,  Man-Tang Wu ,  Jeng-Wei Yang ,  Chien-Sheng Su

    IPC: H01L27/115 ,  H01L29/51 ,  H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02 ,  H01L29/788 ,  H01L29/423 ,  H01L29/45

    CPC classification number: H01L27/11521 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/45 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/511 ,  H01L29/517 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

    Abstract: A non-volatile memory cell includes a substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type spaced apart from the first region, forming a channel region therebetween. A floating gate is disposed over and insulated from a first portion of the channel region which is adjacent the first region. A select gate is disposed over a second portion of the channel region adjacent to the second region, the select gate being formed of a metal material and being insulated from the second portion of the channel region by a layer of silicon dioxide and a layer of high K insulating material. A control gate is disposed over and insulated from the floating gate. An erase gate is disposed over and insulated from the first region, and disposed laterally adjacent to and insulated from the floating gate.

    Abstract translation: 非易失性存储单元包括第一导电类型的衬底，具有第二导电类型的第一区域，与第一区域间隔开的第二导电类型的第二区域，在它们之间形成沟道区域。 浮置栅极设置在与第一区域相邻的沟道区域的第一部分之上并与其绝缘。 选择栅极设置在与第二区域相邻的沟道区域的第二部分上，选择栅极由金属材料形成并且通​​过二氧化硅层和高层与沟道区域的第二部分绝缘 K绝缘材料。 控制栅极设置在浮动栅极上并与浮动栅极绝缘。 擦除栅极设置在第一区域的上方并与第一区域绝缘，并且横向地邻近浮动栅极并与其隔离。

    Method Of Making Embedded Memory Device With Silicon-On-Insulator Substrate
    15.
    发明申请
    Method Of Making Embedded Memory Device With Silicon-On-Insulator Substrate 有权
    使用绝缘体上硅衬底制造嵌入式存储器件的方法

    公开(公告)号：US20160086962A1

    公开(公告)日：2016-03-24

    申请号：US14491596

    申请日：2014-09-19

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Chien-Sheng Su ,  Hieu Van Tran ,  Mandana Tadayoni ,  Nhan Do ,  Jeng-Wei Yang

    IPC: H01L27/115 ,  H01L21/762 ,  H01L29/423 ,  H01L21/306 ,  H01L29/66 ,  H01L29/06

    CPC classification number: H01L27/11531 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/7624 ,  H01L27/11521 ,  H01L27/11534 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/42328 ,  H01L29/66825

    Abstract: A method of forming a semiconductor device starts with a substrate of silicon, a first insulation layer on the silicon, and a silicon layer on the first insulation layer. The silicon layer and the insulation layer are removed just from a second substrate area. A second insulation layer is formed over the silicon layer in the substrate first area and over the silicon in the second substrate area. A first plurality of trenches is formed in the first substrate area that each extends through all the layers and into the silicon. A second plurality of trenches is formed in the second substrate area that each extends through the second insulation layer and into the silicon. An insulation material is formed in the first and second trenches. Logic devices are formed in the first substrate area, and memory cells are formed in the second substrate area.

    Abstract translation: 形成半导体器件的方法从硅衬底，硅上的第一绝缘层和第一绝缘层上的硅层开始。 仅从第二衬底区域去除硅层和绝缘层。 第二绝缘层形成在衬底第一区域中的硅层之上并且在第二衬底区域中的硅上方。 第一多个沟槽形成在第一衬底区域中，每个沟槽延伸穿过所有层并进入硅中。 第二多个沟槽形成在第二衬底区域中，每个沟槽延伸穿过第二绝缘层并进入硅中。 绝缘材料形成在第一和第二沟槽中。 逻辑器件形成在第一衬底区域中，并且存储器单元形成在第二衬底区域中。

    Double patterning method of forming semiconductor active areas and isolation regions
    16.
    发明授权
    Double patterning method of forming semiconductor active areas and isolation regions 有权
    形成半导体有源区和隔离区的双重图案化方法

    公开(公告)号：US09293358B2

    公开(公告)日：2016-03-22

    申请号：US14162309

    申请日：2014-01-23

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Jeng-Wei Yang ,  Chien-Sheng Su

    IPC: H01L21/336 ,  H01L21/762 ,  H01L21/308

    CPC classification number: H01L21/76224 ,  H01L21/3086 ,  H01L21/3088

    Abstract: A method of forming active areas and isolation regions in a semiconductor substrate using a double patterning process. The method include forming a first material on the substrate surface, forming a second material on the first material, forming a plurality of first trenches into the second material wherein the plurality of first trenches are parallel to each other, forming a second trench into the second material wherein the second trench is perpendicular to and crosses the plurality of first trenches in a central region of the substrate, filling the first and second trenches with a third material, removing the second material to form third trenches in the third material that are parallel to each other and do not extend through the central region of the substrate, and extending the third trenches through the first material and into the substrate.

    Abstract translation: 使用双重图案化工艺在半导体衬底中形成有源区和隔离区的方法。 该方法包括在衬底表面上形成第一材料，在第一材料上形成第二材料，在第二材料中形成多个第一沟槽，其中多个第一沟槽彼此平行，形成第二沟槽 材料，其中所述第二沟槽在所述衬底的中心区域中垂直于所述第一沟槽并与所述多个第一沟槽交叉，用第三材料填充所述第一和第二沟槽，移除所述第二材料以在所述第三材料中形成平行于所述第三材料的第三沟槽 彼此不延伸穿过衬底的中心区域，并且延伸第三沟槽穿过第一材料并进入衬底。

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