公开(公告)号：US20150372058A1

公开(公告)日：2015-12-24

申请号：US14839409

申请日：2015-08-28

Applicant: SK hynix Inc.

Inventor： Hae Chan PARK

IPC: H01L27/24 ,  H01L45/00 ,  H01L21/3213 ,  H01L29/08 ,  H01L21/02 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L27/2454 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0455 ,  H01L21/32139 ,  H01L27/101 ,  H01L29/0847 ,  H01L29/42356 ,  H01L29/66666 ,  H01L29/7827 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1675

Abstract: A method for fabricating a semiconductor apparatus includes forming a diffusion barrier film on a semiconductor substrate, forming a first film on a semiconductor substrate including a common source region, forming a second film on the first film, forming a conductive film on the second film, patterning the conductive film and the second film, to form an active pattern, and patterning the first film and the semiconductor substrate using the active pattern as a mask, to form a pillar; and forming a gate electrode on an outer circumference of the pillar.

Abstract translation: 一种制造半导体装置的方法，包括在半导体衬底上形成扩散阻挡膜，在包括公共源极区域的半导体衬底上形成第一膜，在第一膜上形成第二膜，在第二膜上形成导电膜， 图案化导电膜和第二膜，以形成有源图案，并且使用活性图案作为掩模对第一膜和半导体基板进行图案化以形成柱; 以及在所述柱的外周上形成栅电极。

公开(公告)号：US20150357377A1

公开(公告)日：2015-12-10

申请号：US14477574

申请日：2014-09-04

Applicant: SK hynix Inc.

Inventor： Hae Chan PARK

IPC: H01L27/24 ,  H01L49/02 ,  H01L29/40

CPC classification number: H01L27/2436 ,  H01L27/0805 ,  H01L28/60 ,  H01L29/66181 ,  H01L29/94

Abstract: A semiconductor integrated circuit device having a reservoir capacitor and a method of manufacturing the same are provided. A first insulating layer is formed on a semiconductor substrate including a first region and a second region. A first conductive layer is formed on the first insulating layer, and a second insulating layer is formed on the first conductive layer. The second insulating layer is patterned to be left in a portion of the first region. A second conductive layer is formed on the second insulating layer and the first conductive layer. The second conductive layer is etched to expose a partial surface of the first conductive layer in the first region. The second conductive layer and the first conductive layer are etched to form a reservoir capacitor in the first region and form a gate in the second region.

Abstract translation: 提供一种具有储存电容器的半导体集成电路器件及其制造方法。 在包括第一区域和第二区域的半导体衬底上形成第一绝缘层。 在第一绝缘层上形成第一导电层，在第一导电层上形成第二绝缘层。 图案化第二绝缘层以留在第一区域的一部分中。 第二导电层形成在第二绝缘层和第一导电层上。 蚀刻第二导电层以暴露第一区域中的第一导电层的部分表面。 蚀刻第二导电层和第一导电层以在第一区域中形成储存电容器，并在第二区域中形成栅极。

公开(公告)号：US20150357037A1

公开(公告)日：2015-12-10

申请号：US14831269

申请日：2015-08-20

Applicant: SK hynix Inc.

Inventor： Hae Chan PARK

IPC: G11C13/00

CPC classification number: G11C13/0038 ,  G11C13/0004

Abstract: A high voltage generating circuit for a resistive memory apparatus is provided. The high voltage generating circuit includes a capacitor spaced from a semiconductor substrate and electrically insulated from the semiconductor substrate. A switching device, which is electrically connected to the capacitor, is electrically insulated from the semiconductor substrate.

Abstract translation: 提供了一种用于电阻式存储装置的高电压产生电路。 高电压发生电路包括与半导体衬底间隔开并与半导体衬底电绝缘的电容器。 电连接到电容器的开关器件与半导体衬底电绝缘。

公开(公告)号：US20150109856A1

公开(公告)日：2015-04-23

申请号：US14158496

申请日：2014-01-17

Applicant: SK hynix Inc.

Inventor： Seung Yun LEE ,  Hae Chan PARK ,  Myoung Sub KIM ,  Se Ho LEE

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C7/04 ,  G11C13/0004 ,  G11C13/0033 ,  G11C2013/008

Abstract: A semiconductor memory apparatus and a temperature control method thereof are provided. The semiconductor memory apparatus includes a temperature adjustment unit suitable for adjusting a temperature of a memory cell, and a temperature control unit suitable for sensing a temperature of the temperature adjustment unit, comparing a sensed temperature with a reference temperature range, and controlling the temperature adjustment unit to adjust the temperature thereof within the reference temperature range based on a comparison result.

Abstract translation: 提供半导体存储装置及其温度控制方法。 半导体存储装置包括适于调节存储单元的温度的温度调节单元，以及温度调节单元，其适于感测温度调节单元的温度，将感测温度与参考温度范围进行比较，并且控制温度调节 基于比较结果在基准温度范围内调节其温度。

公开(公告)号：US20150009753A1

公开(公告)日：2015-01-08

申请号：US14494382

申请日：2014-09-23

Applicant: SK hynix Inc.

Inventor： Hae Chan PARK ,  Se Ho Lee

IPC: G11C13/00

CPC classification number: G11C13/0004 ,  G11C11/21 ,  G11C11/5678 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0042 ,  G11C2013/0078 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  H01L45/04

Abstract: A phase change memory device having a multi-level and a method of driving the same are presented. The disclosed phase change memory device includes variable resistors and shifting units. The variable resistors are interchanged into set and reset states in response to an applied current. The shifting units, which are connected to the variable resistors, shift resistance distribution in the set and reset state of the variable resistors by a predetermined level.

Abstract translation: 提出了具有多级的相变存储器件及其驱动方法。 所公开的相变存储器件包括可变电阻器和变换单元。 响应于所施加的电流，可变电阻器被互换成置位和复位状态。 连接到可变电阻器的变速单元将可变电阻器的设定和复位状态下的电阻分布移位预定水平。

公开(公告)号：US20140286089A1

公开(公告)日：2014-09-25

申请号：US14297213

申请日：2014-06-05

Applicant: SK HYNIX INC.

Inventor： Hae Chan PARK ,  Soo Gil KIM

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C11/00 ,  G11C13/0004 ,  G11C13/0033 ,  G11C2013/0092 ,  Y10S977/754

Abstract: A semiconductor integrated circuit system includes a phase-change line including a first phase-change area constituting a first memory cell and a second phase-change area constituting a second memory cell, a write current providing unit configured to phase-change a selected one of the first and second phase-change areas, and a phase-change compensation unit configured to restore the other of the first and second phase-change areas by compensating for a dummy phase-change caused in the other phase-change area due to a phase-change of the selected phase-change area.

Abstract translation: 一种半导体集成电路系统包括：相变线，包括构成第一存储单元的第一相变区和构成第二存储单元的第二相变区;写入电流提供单元，被配置为对 第一相变区和第二相变区，以及相变补偿单元，被配置为通过补偿由于相位而在另一个相变区域中引起的虚拟相位变化来恢复第一和第二相变区域中的另一个 - 所选择的相变区域的更换。

公开(公告)号：US20140166965A1

公开(公告)日：2014-06-19

申请号：US13846129

申请日：2013-03-18

Applicant: SK HYNIX INC.

Inventor： Jung Won SEO ,  Hae Chan PARK ,  Myoung Sub KIM ,  Sung Bin HONG ,  Se Ho LEE ,  Seung Yun LEE

IPC: H01L45/00

CPC classification number: H01L45/06 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/124 ,  H01L45/1608 ,  H01L45/1666

Abstract: A resistive memory device may include a bottom structure, a memory cell structure disposed on the bottom structure, and a data storage material disposed to surround an outer sidewall of the memory cell structure.

Abstract translation: 电阻式存储器件可以包括底部结构，设置在底部结构上的存储单元结构，以及设置成围绕存储单元结构的外侧壁的数据存储材料。

公开(公告)号：US20130146831A1

公开(公告)日：2013-06-13

申请号：US13753610

申请日：2013-01-30

Applicant: SK HYNIX INC.

Inventor： Hae Chan PARK

IPC: H01L45/00

CPC classification number: H01L27/2409 ,  H01L29/861 ,  H01L45/06

Abstract: A phase-change memory device with an improved current characteristic is provided. The phase-change memory device includes a metal word line, a semiconductor layer of a first conductivity type being in contact with the metal word line, and an auxiliary diode layer being in contact with metal word line and the semiconductor layer,

Abstract translation: 提供了具有改善的电流特性的相变存储器件。 相变存储器件包括金属字线，与金属字线接触的第一导电类型的半导体层和与金属字线和半导体层接触的辅助二极管层，

公开(公告)号：US20190115425A1

公开(公告)日：2019-04-18

申请号：US16210737

申请日：2018-12-05

Applicant: SK hynix Inc.

Inventor： Hae Chan PARK ,  Jae Taek KIM

IPC: H01L29/06 ,  H01L23/528

CPC classification number: H01L29/0649 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/2481 ,  H01L27/249 ,  H01L29/40117 ,  H01L45/04 ,  H01L45/06 ,  H01L45/10 ,  H01L45/1233

Abstract: A semiconductor device includes a stack structure located on a substrate and includes a first region, in which sacrificial layers and insulating layers are alternately stacked, and a second region, in which conductive layers and insulating layers are alternately stacked. The stack structure also includes a first slit insulating layer located at a boundary between the first region and the second region, wherein the first slit insulating layer penetrates the stack structure and extends in one direction. The stack structure further includes a plurality of slit insulating patterns located in the second region, wherein the plurality of slit insulating patterns penetrate the stack structure and are arranged along the one direction. At least one conductive layer among the conductive layers is bent between the first slit insulating layer and the slit insulating patterns.

公开(公告)号：US20170162262A1

公开(公告)日：2017-06-08

申请号：US15434458

申请日：2017-02-16

Applicant: SK hynix Inc.

Inventor： Hae Chan PARK ,  Myoung Sub KIM ,  Se Ho LEE ,  Seung Yun LEE

IPC: G11C13/00 ,  G11C11/56

CPC classification number: G11C13/003 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/15 ,  G11C2213/73

Abstract: A resistive memory device includes a memory cell array including a unit memory cell coupled between a word line and a bit line, wherein the unit memory cell includes a data storage material and a non-silicon-substrate-based type bidirectional access device coupled in series, a path setting circuit coupled between the bit line and the word line, suitable for providing a program pulse toward the bit line or the word line based on a path control signal, a forward write command, and a reverse write command, and a control unit suitable for providing a write path control signal, a forward program command, and a reverse program command based on an external command signal.