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    SEMICONDUCTOR DEVICE WITH OTP MEMORY CELL
    12.
    发明申请
    SEMICONDUCTOR DEVICE WITH OTP MEMORY CELL 有权
    具有OTP存储单元的半导体器件

    公开(公告)号：US20130077377A1

    公开(公告)日：2013-03-28

    申请号：US13624255

    申请日：2012-09-21

    Applicant: SK hynix Inc.

    Inventor： Tae Hoon Kim

    IPC: G11C17/08

    CPC classification number: G11C17/08 ,  G11C17/00 ,  G11C17/16

    Abstract: A semiconductor device includes a one-time programmable (OTP) memory cell includes a first MOS transistor having a gate coupled to a bit line, a first switching device, coupled to one side of a source/drain of the first MOS transistor, configured to provide a current path for a current supplied to the gate of the first MOS transistor, and a second switching device configured to provide a bias voltage at the other side of the source/drain of the first MOS transistor.

    Abstract translation: 半导体器件包括一次性可编程（OTP）存储单元，其包括具有耦合到位线的栅极的第一MOS晶体管，耦合到第一MOS晶体管的源极/漏极的一侧的第一开关器件，被配置为 为提供给第一MOS晶体管的栅极的电流提供电流路径，以及被配置为在第一MOS晶体管的源极/漏极的另一侧提供偏置电压的第二开关器件。

    Semiconductor package including vertical interconnector
    13.
    发明授权
    Semiconductor package including vertical interconnector 有权

    公开(公告)号：US11784162B2

    公开(公告)日：2023-10-10

    申请号：US17154705

    申请日：2021-01-21

    Applicant: SK hynix Inc.

    Inventor： Tae Hoon Kim ,  Chae Sung Lee

    IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

    CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2225/06562

    Abstract: A semiconductor package includes at least one semiconductor chip disposed in such a way that an active surface with chip pads faces a redistribution layer, vertical interconnectors extending in a vertical direction from the chip pads toward the redistribution layer, wherein each of the vertical connectors has a first end portion that is connected to a corresponding chip pad and a second end portion that is disposed on an opposite end of each vertical interconnector in relation to the first end portion, and a molding layer covering the semiconductor chip and the vertical interconnectors while exposing a surface of each of the second end portions of the vertical interconnectors, wherein the redistribution layer is formed over the molding layer, the redistribution layer having a redistribution land that is in contact with the surface of the second end portion, and wherein a width of the surface of the second end portion is greater than a width of an extension portion between the first end portion and the second end portion of each vertical interconnector.

    Electronic device and method for manufacturing electronic device
    14.
    发明授权
    Electronic device and method for manufacturing electronic device 有权

    公开(公告)号：US11437437B2

    公开(公告)日：2022-09-06

    申请号：US16860686

    申请日：2020-04-28

    Applicant: SK hynix Inc.

    Inventor： Si Jung Yoo ,  Tae Hoon Kim ,  Hyung Dong Lee

    IPC: H01L27/24 ,  H01L27/22 ,  H01L45/00 ,  H01L43/12 ,  H01L43/02

    Abstract: An electronic device includes a semiconductor memory including material layers each including one or more low-resistance areas and one or more high-resistance areas, insulating layers stacked alternately with the material layers and including protrusions extending more than the material layers, conductive pillars passing through the insulating layers and the low-resistance areas, conductive layers located between the protrusions, and variable resistance layers interposed between the low-resistance areas and the conductive layers.

    Data storage device and method of programming memory cells
    16.
    发明授权
    Data storage device and method of programming memory cells 有权

    公开(公告)号：US09691486B2

    公开(公告)日：2017-06-27

    申请号：US14947567

    申请日：2015-11-20

    Applicant: SK hynix Inc.

    Inventor： Tae Hoon Kim

    IPC: G11C16/12 ,  G11C11/56 ,  G11C16/34 ,  G11C29/42 ,  G11C29/52 ,  G11C16/04 ,  G11C29/04

    CPC classification number: G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3459 ,  G11C29/42 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2211/5621 ,  G11C2211/5644

    Abstract: A method of programming a non-volatile memory device includes programming memory cells selected from the plurality of memory cells by increasing turn values of program loops based on an incremental step pulse program (ISPP) algorithm; detecting a first turn value of a first program loop wherein, in the first program loop, a first number or a first ratio of first unprogrammed memory cells is smaller than or equal to a first set value; calculating a second turn value of a second program loop based on the first turn value wherein, in the second program loop, a second number or a second ratio of second unprogrammed memory cells is expected to be smaller than or equal to a second set value, the second set value being smaller than the first set value; executing subsequent program loops on the unprogrammed memory cells up to the second program loop; detecting a third number or a third ratio of third unprogrammed memory cells in the second program loop; comparing the third number or the third ratio of the third unprogrammed memory cells to the second set value; determining a program pass when the third number or the third ratio of the third unprogrammed memory cells is smaller than or equal to the second set value; and determining a program fail when the third number or the third ratio of the unprogrammed memory cell exceeds the second set value.

    Semiconductor memory device and method of operating the same
    17.
    发明授权
    Semiconductor memory device and method of operating the same 有权
    半导体存储器件及其操作方法

    公开(公告)号：US09406402B2

    公开(公告)日：2016-08-02

    申请号：US14292299

    申请日：2014-05-30

    Applicant: SK hynix Inc.

    Inventor： Tae Hoon Kim

    IPC: G11C29/50 ,  G11C16/34 ,  G11C11/56 ,  G11C16/26

    CPC classification number: G11C29/50004 ,  G11C11/5642 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  G11C29/12005 ,  G11C29/36 ,  G11C29/38 ,  G11C29/44 ,  G11C2029/5004

    Abstract: A semiconductor memory device and a method of operating the same are provided. The method of operating the semiconductor memory device includes detecting a first group of changed bits between first and second page data, by comparing the first and second page data, which are read out using first and second test voltages from the memory cells, respectively, detecting a second group of changed bits between the second page data and a third page data, by comparing the second page data with the third page data read out from the memory cells using a third test voltage, comparing the numbers of the first and second groups of changed bits, and determining one of the first to third test voltages as a read voltage according to the comparing of the numbers of the first and second groups of changed bits.

    Abstract translation: 提供一种半导体存储器件及其操作方法。 操作半导体存储器件的方法包括通过比较分别使用来自存储器单元的第一和第二测试电压读出的第一和第二页数据来检测第一和第二页数据之间的第一组改变位，检测 通过使用第三测试电压比较第二页面数据和从存储器单元读出的第三页面数据，比较第一和第二组数据的第二组数据， 根据第一组和第二组改变的比特的数量的比较，将第一至第三测试电压之一确定为读取电压。

    Data storage system and method of operating the same
    18.
    发明授权
    Data storage system and method of operating the same 有权
    数据存储系统及其操作方法

    公开(公告)号：US09159429B2

    公开(公告)日：2015-10-13

    申请号：US14163762

    申请日：2014-01-24

    Applicant: SK hynix Inc.

    Inventor： Tae Hoon Kim

    IPC: G11C16/06 ,  G11C16/10

    CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/22

    Abstract: A data storage system and a method of operating the same are provided. The method includes performing a program operation on a first page of the pages of a memory block, deciding, when power is switched on after a sudden power-off is generated while the program operation is performed, whether to skip the program operation on a first erase page of the pages based on a second page on which the program operation is performed subsequent to the first page, and performing the program operation on the second page.

    Abstract translation: 提供了一种数据存储系统及其操作方法。 该方法包括在存储器块的页面的第一页上执行编程操作，决定在执行程序操作时在产生突然断电后何时接通电源时，是否首先跳过程序操作 基于在第一页之后执行程序操作的第二页，擦除页面的页面，并且在第二页面上执行程序操作。

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME
    19.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME 有权
    半导体存储器件及其操作方法

    公开(公告)号：US20140063984A1

    公开(公告)日：2014-03-06

    申请号：US13716412

    申请日：2012-12-17

    Applicant: SK HYNIX INC.

    Inventor： Tae Hoon Kim

    IPC: G11C7/00

    CPC classification number: G11C7/00 ,  G11C11/56 ,  G11C11/5628

    Abstract: A semiconductor memory device is provided. The semiconductor memory device includes memory cells having first to fourth middle states corresponding to different threshold voltage distributions. The semiconductor memory device also includes a peripheral circuit configured to perform a first program operation to program memory cells having the third and the fourth middle states to have four upper states and perform a second program operation to program memory cells having the first and the second middle states to have another four upper states.

    Abstract translation: 提供半导体存储器件。 半导体存储器件包括具有对应于不同阈值电压分布的第一至第四中间状态的存储器单元。 半导体存储器件还包括外围电路，其被配置为执行第一编程操作以对具有第三和第四中间状态的存储单元编程以具有四个上状态，并执行第二编程操作以对具有第一和第二中间状态的存储单元 说有另外四个上层州。

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