公开(公告)号：US09806016B2

公开(公告)日：2017-10-31

申请号：US15068877

申请日：2016-03-14

Applicant: SK hynix Inc.

Inventor： Jong Hoon Kim ,  Han Jun Bae ,  Chan Woo Jeong

IPC: H01L29/06 ,  H01L23/498 ,  H01L23/29 ,  H01L23/00

CPC classification number: H01L23/4985 ,  H01L23/293 ,  H01L23/298 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/562 ,  H01L24/32 ,  H01L2224/32013 ,  H01L2224/32057 ,  H01L2224/32238

Abstract: A semiconductor package includes an extendible molding member, a chip embedded in the molding member to have a warped shape, and connectors disposed in the molding member. First surfaces of the connectors are exposed at a surface of the molding member, and second surfaces of the connectors are coupled to the chip.

公开(公告)号：US09659833B2

公开(公告)日：2017-05-23

申请号：US14808596

申请日：2015-07-24

Applicant: SK hynix Inc.

Inventor： Dae Woong Lee ,  Tae Min Kang ,  Han Jun Bae

IPC: H01L23/29 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/293 ,  H01L21/563 ,  H01L23/296 ,  H01L23/3142 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/04042 ,  H01L2224/26145 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83365 ,  H01L2224/83855 ,  H01L2224/83856 ,  H01L2224/92247 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/181 ,  H01L2924/182 ,  H01L2924/186 ,  H01L2924/3512 ,  H01L2924/37001 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/0715

Abstract: A semiconductor package includes an adhesive member disposed on a package substrate to have a trapezoid cross-section view, and a semiconductor chip disposed on the adhesive member and attached to the package substrate by the adhesive member. The semiconductor chip has a first surface and a second surface facing the first surface, and the second surface of the semiconductor chip contacts the adhesive member. The semiconductor chip includes a tension supplement pattern attached to the second surface and spaced apart from the package substrate.

公开(公告)号：US09368482B2

公开(公告)日：2016-06-14

申请号：US14935105

申请日：2015-11-06

Applicant: SK hynix Inc.

Inventor： Jong Hoon Kim ,  Han Jun Bae

IPC: H01L23/48 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/05605 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/05618 ,  H01L2224/05623 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/11462 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/81203 ,  H01L2224/81898 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/15311 ,  H01L2224/81

Abstract: Stack packages are provided. The stack package includes a first chip configured to include a first chip body having a top surface and a bottom surface, first through electrodes penetrating the first chip body, and an insulation layer disposed on the bottom surface of the first chip body, and first bumps disposed on the top surface of the first chip body, and a second chip configured to include a second chip body having a top surface and a bottom surface, and second bumps disposed on the top surface of the second chip body. The first and second chips are vertically stacked such that the top surface of the second chip body is directly attached to the first insulation layer and the second bumps of the second chip penetrate the first insulation layer of the first chip to pierce the first through electrodes of the first chip.

Abstract translation: 提供堆栈包。 堆叠封装包括第一芯片，其构造成包括具有顶表面和底表面的第一芯片主体，第一穿透电极穿过第一芯片主体的绝缘层，以及设置在第一芯片主体的底表面上的绝缘层， 设置在第一芯片主体的上表面上，第二芯片构造成包括具有顶表面和底表面的第二芯片主体，以及设置在第二芯片主体的顶表面上的第二凸块。 第一芯片和第二芯片被垂直堆叠，使得第二芯片主体的顶表面直接附接到第一绝缘层，并且第二芯片的第二凸块穿透第一芯片的第一绝缘层以刺穿第一芯片主体的第一穿透电极 第一个芯片。

公开(公告)号：US09343439B2

公开(公告)日：2016-05-17

申请号：US14884864

申请日：2015-10-16

Applicant: SK hynix Inc.

Inventor： Jin Ho Bae ,  Han Jun Bae

IPC: H01L23/48 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3121 ,  H01L24/24 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/06135 ,  H01L2224/24145 ,  H01L2224/24146 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73217 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/92135 ,  H01L2224/92164 ,  H01L2224/92244 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06568 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A stack package includes a substrate having connection terminals and a first chip on the substrate. The first chip has first connectors on edges thereof. A second chip is stacked on the first chip to expose outer portions of the first connectors. The second chip has second connectors on edges thereof. Connection members to connect the exposed outer portions of the first connectors to the connection terminals. Sidewall interconnectors to connect the exposed outer portions of the first connectors to the second connectors. The sidewall interconnectors extend from the exposed outer portions of the first connectors along sidewalls of the second chip to cover the second connectors.