公开(公告)号：US20180033878A1

公开(公告)日：2018-02-01

申请号：US15436819

申请日：2017-02-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: H01L29/74 ,  H01L29/866 ,  H01L27/02

CPC classification number: H01L29/7412 ,  H01L27/0248 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0262 ,  H01L29/7408 ,  H01L29/866 ,  H02H9/046

Abstract: An integrated circuit includes at least one input-output pad and a terminal intended to be connected to a source of a reference potential and further including a protection structure including a thyristor forward-connected between the pad and the terminal. The thyristor includes a first resistor between its cathode gate and the terminal. At least one Zener diode is disposed between the thyristor and the pad. The anode of the Zener diode is connected to the cathode gate of the thyristor and the cathode of the Zener diode is connected to the pad via at least one second resistor. The junction of the Zener diode is different from the junctions of the PNPN structure of the thyristor.

公开(公告)号：US09779815B2

公开(公告)日：2017-10-03

申请号：US15221318

申请日：2016-07-27

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11521 ,  H01L29/788 ,  H01L27/11526

CPC classification number: G11C16/0408 ,  G11C16/0441 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11521 ,  H01L27/11526 ,  H01L29/7883

Abstract: A method can be used for writing in a memory location of the electrically-erasable and programmable memory type. The memory location includes a first memory cell with a first transistor having a first gate dielectric underlying a first floating gate and a second memory cell with a second transistor having a second gate dielectric underlying a second floating gate that is connected to the first floating gate. In a first writing phase, an identical tunnel effect is implemented through the first gate dielectric and the second gate dielectric. In a second writing phase, a voltage across the first gate dielectric but not the second gate dielectric is increased.

公开(公告)号：US09753665B2

公开(公告)日：2017-09-05

申请号：US15053950

申请日：2016-02-25

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0688 ,  G11C5/066 ,  G11C7/10 ,  G11C8/12

Abstract: A memory device includes an input/output interface, a bus of SPI type coupled to the input/output interface, and a plurality of individual non-volatile memory devices connected to the bus of SPI type. The chip select inputs of each individual memory device are all connected to one and the same chip select wire of the SPI bus. The individual memory devices are further configured and controllable so as to behave, as seen by the input/output interface, as a single non-volatile memory device, the total memory space of which has a total memory capacity equal to the sum of the individual memory capacities of the individual devices.

公开(公告)号：US09747053B1

公开(公告)日：2017-08-29

申请号：US15221343

申请日：2016-07-27

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: G11C16/04 ,  G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/12

Abstract: A memory device of the non-volatile electrically-erasable and programmable memory type is provided. The memory device includes a matrix memory plane of memory cells connected to bit lines. Programming circuitry is configured to select a memory cell and to apply a programming pulse to the corresponding bit line. The memory plane is disposed in a local well at a floating potential and the programming circuitry is configured to increase the potential of the local well simultaneously with the application of the programming pulse to the bit line of a selected memory cell.

公开(公告)号：US20170092357A1

公开(公告)日：2017-03-30

申请号：US15054015

申请日：2016-02-25

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C13/00

CPC classification number: G11C13/0097 ,  G11C5/144 ,  G11C13/0069 ,  G11C16/10 ,  G11C16/14 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3418 ,  G11C29/12005

Abstract: A method of controlling a cycle for writing at least one data item to at least one memory slot of the electrically programmable and erasable read-only memory type disposed in an electronic circuit supplied by a supply voltage includes a controlled increase of the duration of the write cycle in the presence of a decrease in the supply voltage.

公开(公告)号：US09583193B2

公开(公告)日：2017-02-28

申请号：US14864354

申请日：2015-09-24

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/14 ,  G11C16/26 ,  G11C16/10 ,  G11C16/12 ,  H01L27/115

CPC classification number: G11C16/0483 ,  G11C16/0408 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L27/11519 ,  H01L27/11534 ,  H01L29/7881

Abstract: Integrated non-volatile memory device includes an integrated memory cell of the EEPROM type with a floating-gate transistor and a selection transistor connected in series between a source line and a bit line, and a programming circuit for the memory cell. The selection transistor is connected between the floating-gate transistor and the source line. The programming circuit is configured for programming the at least one memory cell with a programming voltage split between a positive voltage and a negative voltage.

Abstract translation: 集成的非易失性存储器件包括具有浮置栅极晶体管的EEPROM类型的集成存储器单元和串联连接在源极线和位线之间的选择晶体管，以及用于存储器单元的编程电路。 选择晶体管连接在浮栅晶体管和源极线之间。 编程电路被配置为用在正电压和负电压之间分压的编程电压对所述至少一个存储器单元进行编程。

公开(公告)号：US20140351489A1

公开(公告)日：2014-11-27

申请号：US14282857

申请日：2014-05-20

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: G11C14/00

CPC classification number: G11C14/0063 ,  G11C7/1042 ,  G11C16/08 ,  G11C16/10

Abstract: A method for writing data into an EEPROM connected to an I2C bus, wherein the data to be written is transmitted in frames having a size corresponding to the size of a physical half-page of the memory. The programming of a data page in the memory is performed while another page is being received.

Abstract translation: 一种将数据写入连接到I2C总线的EEPROM的方法，其中要写入的数据以具有与存储器的物理半页大小对应的大小的帧传输。 在接收另一个页面的同时执行存储器中的数据页面的编程。

公开(公告)号：US12052861B2

公开(公告)日：2024-07-30

申请号：US18321487

申请日：2023-05-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: H01L21/00 ,  G11C7/18 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H10B41/00 ,  H10B41/35 ,  H01L29/788

CPC classification number: H10B41/00 ,  G11C7/18 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66825 ,  H10B41/35 ,  H01L29/7881

Abstract: An EEPROM memory integrated circuit includes memory cells arranged in a memory plane. Each memory cell includes an access transistor in series with a state transistor. Each access transistor is coupled, via its source region, to the corresponding source line and each state transistor is coupled, via its drain region, to the corresponding bit line. The floating gate of each state transistor rests on a dielectric layer having a first part with a first thickness, and a second part with a second thickness that is less than the first thickness. The second part is located on the source side of the state transistor.

公开(公告)号：US20210249086A1

公开(公告)日：2021-08-12

申请号：US17166107

申请日：2021-02-03

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  G11C16/04

Abstract: The memory device of the electrically-erasable programmable read-only memory type comprises write circuitry designed to carry out a write operation in response to receiving a command for writing at least one selected byte in at least one selected memory word of the memory plane, the write operation comprising an erase cycle followed by a programming cycle, and configured for generating, during the erase cycle, an erase voltage in the memory cells of all the bytes of the at least one selected memory word, and an erase inhibit potential configured, with respect to the erase voltage, for preventing the erasing of the memory cells of the non-selected bytes of the at least one selected memory word, which are not the at least one selected byte.

公开(公告)号：US20200321063A1

公开(公告)日：2020-10-08

申请号：US16824268

申请日：2020-03-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Chama Ameziane El Hassani

IPC: G11C16/32 ,  G11C16/10

Abstract: A method for writing to electrically erasable and programmable non-volatile memory and a corresponding integrated circuit are disclosed. In an embodiment a method includes operatively connecting a filter circuit belonging to a communication interface to an oscillator circuit, wherein the communication interface is physically connected to a bus, generating, by the oscillator circuit, an oscillation signal and regulating the oscillation signal by the filter circuit so as to generate a clock signal for timing a write cycle.