公开(公告)号：US20180145183A1

公开(公告)日：2018-05-24

申请号：US15852826

申请日：2017-12-22

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Marc MANTELLI ,  Stephan NIEL ,  Arnaud REGNIER ,  Francesco LA ROSA ,  Julien DELALLEAU

IPC: H01L29/788 ,  G11C16/04 ,  H01L29/66 ,  G11C16/14 ,  H01L21/266 ,  H01L21/28 ,  H01L21/308 ,  H01L21/306 ,  H01L21/3213 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/11556 ,  H01L29/423

CPC classification number: H01L27/11524 ,  G11C16/0425 ,  G11C16/14 ,  H01L21/266 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/32133 ,  H01L27/11521 ,  H01L27/11553 ,  H01L27/11556 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7883

Abstract: Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.

公开(公告)号：US20240063280A1

公开(公告)日：2024-02-22

申请号：US18230423

申请日：2023-08-04

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Franck JULIEN ,  Julien DELALLEAU ,  Julien DURA ,  Julien AMOUROUX ,  Stephane MONFRAY

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/40

CPC classification number: H01L29/42376 ,  H01L29/7833 ,  H01L29/42368 ,  H01L29/401

Abstract: A MOSFET transistor includes, on a semiconductor layer, a stack of a gate insulator and of a gate region on the gate insulator. The gate region has a first gate portion and a second gate portion between the first gate portion and the gate insulator. The first gate portion has a first length in a first lateral direction of the transistor. The second gate portion has a second length in the first lateral direction that is shorter than the first length.

公开(公告)号：US20220005960A1

公开(公告)日：2022-01-06

申请号：US17366585

申请日：2021-07-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian RIVERO ,  Brice ARRAZAT ,  Julien DELALLEAU ,  Joel METZ

IPC: H01L29/94 ,  H01L29/423 ,  H01L29/788 ,  H01L27/11524 ,  H01L49/02 ,  H01L21/28 ,  H01L21/265

Abstract: A semiconductor substrate includes excavations which form trenches sunk. A capacitive element includes: a first dielectric envelope conforming to sides and bottoms of the trenches; a first semiconductor layer conforming to a surface of the first dielectric envelope in the trenches; a second dielectric envelope conforming to a surface of the first semiconductor layer in the trenches; and a second semiconductor layer conforming to a surface of the second dielectric envelope in the trenches.

公开(公告)号：US20160329490A1

公开(公告)日：2016-11-10

申请号：US15214054

申请日：2016-07-19

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Philippe BOIVIN ,  Julien DELALLEAU

IPC: H01L43/12 ,  H01L27/115 ,  H01L27/22 ,  H01L29/423 ,  H01L21/762 ,  H01L45/00 ,  H01L43/02 ,  H01L43/08 ,  H01L21/265 ,  H01L27/24 ,  H01L29/78

CPC classification number: H01L43/12 ,  H01L21/26513 ,  H01L21/76224 ,  H01L23/528 ,  H01L27/11507 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/2463 ,  H01L29/42356 ,  H01L29/7827 ,  H01L43/02 ,  H01L43/08 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to a method of making a memory on semiconductor substrate, comprising: at least one data line, at least one selection line, at least one reference line, at least one memory cell comprising a select transistor having a control gate connected to the selection line, a first conduction terminal connected to a variable impedance element, the select transistor and the variable impedance element coupling the reference line to the data line, the select transistor comprising an embedded vertical gate produced in a trench formed in the substrate, and a channel region opposite a first face of the trench, between a first deep doped region and a second doped region on the surface of the substrate coupled to the variable impedance element.

Abstract translation: 本公开涉及一种在半导体衬底上制造存储器的方法，包括：至少一条数据线，至少一条选择线，至少一条参考线，至少一个存储单元，包括选择晶体管，其具有连接到 所述选择线，连接到可变阻抗元件的第一导电端子，所述选择晶体管和所述参考线耦合到所述数据线的所述可变阻抗元件，所述选择晶体管包括在形成在所述衬底中的沟槽中产生的嵌入垂直栅极，以及 与沟槽的第一面相对的沟道区，位于耦合到可变阻抗元件的衬底表面上的第一深掺杂区和第二掺杂区之间。

公开(公告)号：US20160013245A1

公开(公告)日：2016-01-14

申请号：US14737372

申请日：2015-06-11

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Philippe BOIVIN ,  Julien DELALLEAU

IPC: H01L27/24 ,  H01L43/08 ,  H01L43/12 ,  H01L45/00 ,  H01L29/78 ,  H01L23/528 ,  H01L29/423 ,  H01L21/265 ,  H01L21/762 ,  H01L27/115 ,  H01L43/02 ,  H01L27/22

CPC classification number: H01L43/12 ,  H01L21/26513 ,  H01L21/76224 ,  H01L23/528 ,  H01L27/11507 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/2463 ,  H01L29/42356 ,  H01L29/7827 ,  H01L43/02 ,  H01L43/08 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to a memory on semiconductor substrate, comprising: at least one data line, at least one selection line, at least one reference line, at least one memory cell comprising a select transistor having a control gate connected to the selection line, a first conduction terminal connected to a variable impedance element, the select transistor and the variable impedance element coupling the reference line to the data line, the select transistor comprising an embedded vertical gate produced in a trench formed in the substrate, and a channel region opposite a first face of the trench, between a first deep doped region and a second doped region on the surface of the substrate coupled to the variable impedance element.

Abstract translation: 本公开涉及一种半导体衬底上的存储器，包括：至少一条数据线，至少一条选择线，至少一条参考线，至少一个存储单元，包括选择晶体管，该选择晶体管具有连接到选择线的控制栅极， 连接到可变阻抗元件的第一导电端子，所述选择晶体管和所述参考线耦合到所述数据线的所述可变阻抗元件，所述选择晶体管包括在形成于所述衬底中的沟槽中产生的嵌入垂直栅极和与所述衬底相对的沟道区域 沟槽的第一面，位于耦合到可变阻抗元件的衬底的表面上的第一深掺杂区域和第二掺杂区域之间。

公开(公告)号：US20150236031A1

公开(公告)日：2015-08-20

申请号：US14625356

申请日：2015-02-18

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Marc MANTELLI ,  Stephan NIEL ,  Arnaud REGNIER ,  Francesco LA ROSA ,  Julien DELALLEAU

IPC: H01L27/115 ,  H01L29/788 ,  G11C16/14 ,  H01L21/3213 ,  H01L21/306 ,  H01L21/308 ,  H01L21/266 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L29/7883 ,  G11C16/0425 ,  G11C16/14 ,  H01L21/266 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/32133 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/11556 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/788

Abstract: The present disclosure relates to a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.

Abstract translation: 本公开涉及一种存储单元，其包括垂直选择栅极，在衬底上方延伸的浮置栅极，其中浮置栅极还在非零重叠距离上延伸到垂直选择栅极的一部分上方，存储器单元包括 注入在与选择栅极相对延伸的垂直沟道区域的相交处的掺杂区域和与浮动栅极相对延伸的水平沟道区域。

公开(公告)号：US20230327028A1

公开(公告)日：2023-10-12

申请号：US18210155

申请日：2023-06-15

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian RIVERO ,  Brice ARRAZAT ,  Julien DELALLEAU ,  Joel METZ

IPC: H01L29/94 ,  H01L21/28 ,  H01L21/265 ,  H01L29/423 ,  H01L29/788 ,  H10B41/35

CPC classification number: H01L29/945 ,  H01L29/40114 ,  H01L21/2652 ,  H01L28/91 ,  H01L29/4236 ,  H01L29/788 ,  H10B41/35

Abstract: A semiconductor substrate includes excavations which form trenches sunk. A capacitive element includes: a first dielectric envelope conforming to sides and bottoms of the trenches; a first semiconductor layer conforming to a surface of the first dielectric envelope in the trenches; a second dielectric envelope conforming to a surface of the first semiconductor layer in the trenches; and a second semiconductor layer conforming to a surface of the second dielectric envelope in the trenches.

公开(公告)号：US20190027581A1

公开(公告)日：2019-01-24

申请号：US16036453

申请日：2018-07-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien DELALLEAU ,  Christian RIVERO

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423

Abstract: A MOS transistor is produced on and in an active zone and included a source region and a drain region. The active zone has a width measured transversely to a source-drain direction. A conductive gate region of the MOS transistor includes a central zone and, at a foot of the central zone, at least one stair that extends beyond the central zone along at least an entirety of the width of the active zone.

公开(公告)号：US20190027565A1

公开(公告)日：2019-01-24

申请号：US16037095

申请日：2018-07-17

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian RIVERO ,  Guilhem BOUTON ,  Pascal FORNARA ,  Julien DELALLEAU

IPC: H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8234 ,  H01L21/28

CPC classification number: H01L29/4238 ,  H01L21/28035 ,  H01L21/28114 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/4983 ,  H01L29/78 ,  H01L29/7833

Abstract: A MOS transistor is produced on and in an active zone which includes a source region and a drain region. The active zone is surrounded by an insulating region. A conductive gate region of the transistor has two flanks which extend transversely to a source-drain direction, and the conductive gate region overlaps two opposite edges of the active zone act overlap zones. The conductive gate region includes, at a location of at least one overlap zone, at least one conductive tag which projects from at least one flank at a foot of the conductive gate region. The conductive tag covers a part of the active zone and a part of the insulating region.

公开(公告)号：US20170084749A1

公开(公告)日：2017-03-23

申请号：US15365768

申请日：2016-11-30

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Marc MANTELLI ,  Stephan NIEL ,  Arnaud REGNIER ,  Francesco LA ROSA ,  Julien DELALLEAU

IPC: H01L29/788 ,  G11C16/04 ,  H01L27/115 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7883 ,  G11C16/0425 ,  G11C16/14 ,  H01L21/266 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/32133 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/11556 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/788

Abstract: Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.